Riscv - #15

Merged

magistermaks merged 18 commits into

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Jun 13, 2026

Commits on May 7, 2026

Created RISC-V language module
magistermaks
committed
9ad13e1
Added basic Risc-V encodings
magistermaks
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4fbecd9

Commits on May 14, 2026

Added some basic Risc-V instructions
magistermaks
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2b5b473

Commits on May 15, 2026

Finish R64 load/stores
magistermaks
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81616df

Commits on May 18, 2026

Add Risc-V branch instructions
magistermaks
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052ffc4
Add Risc-V jump instructions
magistermaks
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19faf0d

Commits on May 19, 2026

Add Risc-V LUI instruction
magistermaks
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9e35e23
Add RV32M extension instructions
magistermaks
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03dfeb5

Commits on May 20, 2026

Finish RV64M extension
magistermaks
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aee1e29
Flexible condition encoding in branaches
magistermaks
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ed5dad8
Added RV32I aliases
magistermaks
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a5d96ae
Register name alises
magistermaks
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8134fd6

Commits on May 23, 2026

Add RV64A extension instructions
magistermaks
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39a6d6e

Commits on May 24, 2026

Test on RiscV (QEMU on Linux)
magistermaks
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d4e8520
Allow RiscV target architecture
magistermaks
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3fcf12a
Add USE_MOLD CMake option
magistermaks
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3970c37
Runtime RiscV test
magistermaks
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f5829fb

Commits on Jun 10, 2026

Use uraimo/run-on-arch-action GHA
magistermaks
committed
671b602