Fix bugs and compilations from toolchain / b9s upgrade

Makefile

@@ -33,7 +33,7 @@ CFLAGS	:=	-g -Wall -Wextra -Wpedantic -Wcast-align -Wno-main -O2\
 
 CFLAGS	+=	$(INCLUDE) -DARM9
 
-CFLAGS	+=	-DBUILD_NAME="\"$(TARGET) (`date +'%Y/%m/%d'`)\""
+CFLAGS	+=	-DBUILD_NAME="\"$(TARGET) `date +'%Y/%m/%d'`\""
 
 ifeq ($(FONT),ORIG)
 CFLAGS	+=	-DFONT_ORIGINAL

source/common/common.h

@@ -54,7 +54,7 @@
 #ifndef OPEN_INSTALLER
 #define APP_TITLE   "SafeB9SInstaller" " v" VERSION
 #define APP_URL     "https://github.com/d0k3/SafeB9SInstaller"
-#define APP_USAGE   "Usage instructions: https://%s3ds.guide/", IS_DEVKIT ? "dev." : ""
+#define APP_USAGE   "Usage instructions: https://%s.hacks.guide/", IS_DEVKIT ? "panda" : "3ds"
 #else
 #define APP_TITLE   "OpenFirmInstaller" " v" VERSION
 #define APP_URL     "https://github.com/d0k3/SafeB9SInstaller"

source/common/memcpy.s

@@ -0,0 +1,72 @@
+@ memcpy_arm946e-s - hand written reimplementation of memcpy to be sequential
+@ Written in 2019 by luigoalma <luigoalma at gmail dot com>
+@ To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
+@ For a copy of CC0 Public Domain Dedication, see <https://creativecommons.org/publicdomain/zero/1.0/>.
+	.cpu    arm946e-s
+	.arch   armv5te
+	.arm
+	.section .text.memcpy, "ax", %progbits
+	.align  2
+	.global memcpy
+	.syntax unified
+	.type   memcpy, %function
+memcpy:
+	@ r0 = dest
+	@ r1 = src
+	@ r2 = length
+	@ check if length 0 and return if so
+	cmp     r2, #0
+	bxeq    lr
+	push    {r0,r4-r9,lr}
+	@ pre-fetch data
+	pld     [r1]
+	@ alignment check with word size
+	@ if not aligned but both are in the same misalignment, fix it up
+	@ otherwise jump to basic loop
+	orr     r12, r0, r1
+	ands    r12, r12, #3
+	beq     .L1
+	and     r4, r0, #3
+	and     r5, r1, #3
+	cmp     r4, r5
+	bne     .L6
+	rsb     r4, r4, #4
+.L0:
+	ldrb    r3, [r1], #1
+	strb    r3, [r0], #1
+	subs    r2, r2, #1
+	popeq   {r0,r4-r9,pc}
+	subs    r4, r4, #1
+	bne     .L0
+.L1:
+	@ check if length higher than 32
+	@ if so, do the 32 byte block copy loop,
+	@ until there's nothing left or remainder to copy is less than 32
+	movs    r3, r2, LSR#5
+	beq     .L3
+.L2:
+	ldm     r1!, {r4-r9,r12,lr}
+	stm     r0!, {r4-r9,r12,lr}
+	subs    r3, r3, #1
+	bne     .L2
+	ands    r2, r2, #0x1F
+	popeq   {r0,r4-r9,pc}
+.L3:
+	@ copy in word size the remaining data,
+	@ and finish off with basic loop if can't copy all by word size.
+	movs    r3, r2, LSR#2
+	beq     .L6
+.L4:
+	ldr     r12, [r1], #4
+	str     r12, [r0], #4
+	subs    r3, r3, #1
+	bne     .L4
+	ands    r2, r2, #0x3
+.L5: @ the basic loop
+	popeq   {r0,r4-r9,pc}
+.L6:
+	ldrb    r3, [r1], #1
+	strb    r3, [r0], #1
+	subs    r2, r2, #1
+	b       .L5
+	.size   memcpy, .-memcpy

source/start.s

@@ -98,6 +98,25 @@ _skip_gw:
     bic r4, #(1<<0)            @ - mpu disable
     mcr p15, 0, r4, c1, c0, 0  @ write control register
 
+    @ Disable FIQs and IRQs
+    msr cpsr_cxsf, #0xD3 @ PSR_SVC_MODE | PSR_I | PSR_F
+
+    @ Disable and acknowledge interrupts
+    mov r2, #0x10000000
+    add r2, r2, #0x1000
+    mov r0, #0
+    mvn r1, #0        @ 0xFFFFFFFF
+    strd r0, r1, [r2] @ REG_IE/IF
+
+    @ Clear NDMA registers
+    add r2, r2, #0x1000 @ NDMA_GLOBAL_CNT, 0x10002000 = 0x10001000 + 0x1000
+    add r1, r2, #0xFC
+    add r2, r2, #0x1C
+    dma_clear_loop:
+        str r0, [r2], #0x1C
+        cmp r1, r2
+        bne dma_clear_loop
+
     @ Clear bss
     ldr r0, =__bss_start
     ldr r1, =__bss_end