bi: ethmac support

bi/src/bi.rs

@@ -786,7 +786,18 @@ impl Thread {
             // only the final assignment to a pin matters
             if !pins_assigned.contains(&pin) {
                 pins_assigned.insert(pin);
-                let pin_expr = ti.pin_exprs[&pin];
+                let pin_expr = *ti.pin_exprs.get(&pin).unwrap_or_else(|| {
+                    panic!(
+                        "pin `{}` ({:?}) not found\navailable: {}",
+                        ti.sym[pin].full_name(&ti.sym),
+                        pin,
+                        ti.pin_exprs
+                            .keys()
+                            .map(|p| ti.sym[p].full_name(&ti.sym).to_string())
+                            .collect::<Vec<_>>()
+                            .join(", ")
+                    )
+                });
                 if let Some(fail) = self.exec_equality(get_value, ti, stmt, pin_expr, expr) {
                     self.failures.push(fail);
                 } else if !matches!(ti.proto[expr], Expr::DontCare) {

bi/src/main.rs

@@ -86,10 +86,18 @@ struct Cli {
     display_hex: bool,
 }
 
-fn get_clock(modules: &[Module], cli_sample_posedge: Option<String>) -> Option<String> {
-    let mut clocks: Vec<String> = modules
+fn get_clock(
+    modules: &[Module],
+    instances: &[Instance],
+    cli_sample_posedge: Option<String>,
+) -> Option<String> {
+    let mut used_modules: Vec<_> = instances.iter().map(|i| i.module_id).collect();
+    used_modules.sort();
+    used_modules.dedup();
+
+    let mut clocks: Vec<String> = used_modules
         .iter()
-        .flat_map(|m| match &m.clock {
+        .flat_map(|&m_id| match &modules[m_id].clock {
             Clock::None => None,
             Clock::Posedge(name) => Some(name.to_string()),
         })
@@ -129,7 +137,6 @@ fn main() {
     let skip_static_step_fork_checks = false;
     let mut d = DiagnosticHandler::new(cli.color, false, show_warnings, false);
     let (st, modules) = frontend(&cli.protocol, &mut d, skip_static_step_fork_checks).unwrap();
-    let posedge_clock = get_clock(&modules, cli.sample_posedge);
 
     // try to find instances that we care about
     if cli.instances.is_empty() {
@@ -144,6 +151,8 @@ fn main() {
         .map(|arg| parse_instance(&modules, arg))
         .collect();
 
+    let posedge_clock = get_clock(&modules, &instances, cli.sample_posedge);
+
     let bi_protos: Vec<Vec<_>> = instances
         .iter()
         .map(|inst| modules[inst.module_id].protos.clone())

cli/src/main.rs

@@ -32,7 +32,10 @@ enum Cmds {
     /// Print out all the constructs used in each protocol
     Constructs,
     /// Prints out the protocols after the frontend processing
-    Show,
+    Show {
+        #[arg(long, help = "only include these modules")]
+        include: Vec<String>,
+    },
     Verilog {
         verilog_tb: String,
         #[arg(long)]
@@ -180,8 +183,17 @@ fn run_verilog_tb(
         .unwrap();
 }
 
-fn show(st: &SymbolTable, modules: &[Module]) {
-    serialize_modules(&mut std::io::stdout(), st, modules).unwrap();
+fn show(st: &SymbolTable, modules: &[Module], include: &[String]) {
+    if include.is_empty() {
+        serialize_modules(&mut std::io::stdout(), st, modules).unwrap();
+    } else {
+        let modules: Vec<_> = modules
+            .iter()
+            .filter(|m| include.contains(&m.name))
+            .cloned()
+            .collect();
+        serialize_modules(&mut std::io::stdout(), st, &modules).unwrap();
+    }
 }
 
 fn main() {
@@ -202,8 +214,8 @@ fn main() {
                 }
             }
         }
-        Some(Cmds::Show) => {
-            show(&st, &modules);
+        Some(Cmds::Show { include }) => {
+            show(&st, &modules, &include);
         }
         Some(Cmds::Verilog {
             verilog_tb,

examples/wishbone/ethmac.prot

@@ -0,0 +1,112 @@
+// --instances tb_ethernet.eth_top.wishbone:Tb_ethernetEth_topWishboneMWb --wave wishbone/ethmac/ethmac.fst
+module Tb_ethernetEth_topWishboneMWb : Wishbone {
+  in WB_CLK_I : clock @posedge,
+  in Reset : u1 = Wishbone.RST,
+  in m_wb_adr_o : u30 = Wishbone.ADR[31:2] with Wishbone.ADR[1:0] == 2'd0,
+  out m_wb_dat_i : u32 = Wishbone.DAT_I,
+  in m_wb_dat_o : u32 = Wishbone.DAT_O,
+  in m_wb_we_o : u1 = Wishbone.WE,
+  in m_wb_stb_o : u1 = Wishbone.STB,
+  in m_wb_cyc_o : u1 = Wishbone.CYC,
+  out m_wb_ack_i : u1 = Wishbone.ACK,
+  in m_wb_sel_o : u4 = Wishbone.SEL,
+  out m_wb_err_i : u1 = Wishbone.ERR,
+  in m_wb_cti_o : u3 = Wishbone.CTI,
+  in m_wb_bte_o : u2 = Wishbone.BTE,
+}
+
+// --instances tb_ethernet.eth_top:Tb_ethernetEth_topMWb --wave wishbone/ethmac/ethmac.fst
+module Tb_ethernetEth_topMWb : Wishbone {
+  in wb_clk_i : clock @posedge,
+  in wb_rst_i : u1 = Wishbone.RST,
+  in m_wb_adr_o : u32 = Wishbone.ADR,
+  out m_wb_dat_i : u32 = Wishbone.DAT_I,
+  in m_wb_dat_o : u32 = Wishbone.DAT_O,
+  in m_wb_we_o : u1 = Wishbone.WE,
+  in m_wb_stb_o : u1 = Wishbone.STB,
+  in m_wb_cyc_o : u1 = Wishbone.CYC,
+  out m_wb_ack_i : u1 = Wishbone.ACK,
+  in m_wb_sel_o : u4 = Wishbone.SEL,
+  out m_wb_err_i : u1 = Wishbone.ERR,
+  in m_wb_cti_o : u3 = Wishbone.CTI,
+  in m_wb_bte_o : u2 = Wishbone.BTE,
+}
+
+// --instances tb_ethernet.wb_master.wbm_low_level:Tb_ethernetWb_masterWbm_low_level --wave wishbone/ethmac/ethmac.fst
+module Tb_ethernetWb_masterWbm_low_level : Wishbone {
+  in CLK_I : clock @posedge,
+  in RST_I : u1 = Wishbone.RST,
+  in ADR_O : u32 = Wishbone.ADR,
+  out DAT_I : u32 = Wishbone.DAT_I,
+  in DAT_O : u32 = Wishbone.DAT_O,
+  in WE_O : u1 = Wishbone.WE,
+  in STB_O : u1 = Wishbone.STB,
+  in CYC_O : u1 = Wishbone.CYC,
+  out ACK_I : u1 = Wishbone.ACK,
+  in SEL_O : u4 = Wishbone.SEL,
+  out ERR_I : u1 = Wishbone.ERR,
+  // out RTY_I : u1 = Wishbone.RTY,
+}
+
+// --instances tb_ethernet.wb_master:Tb_ethernetWb_master --wave wishbone/ethmac/ethmac.fst
+module Tb_ethernetWb_master : Wishbone {
+  in CLK_I : clock @posedge,
+  in RST_I : u1 = Wishbone.RST,
+  in ADR_O : u32 = Wishbone.ADR,
+  out DAT_I : u32 = Wishbone.DAT_I,
+  in DAT_O : u32 = Wishbone.DAT_O,
+  in WE_O : u1 = Wishbone.WE,
+  in STB_O : u1 = Wishbone.STB,
+  in CYC_O : u1 = Wishbone.CYC,
+  out ACK_I : u1 = Wishbone.ACK,
+  in SEL_O : u4 = Wishbone.SEL,
+  out ERR_I : u1 = Wishbone.ERR,
+  // out RTY_I : u1 = Wishbone.RTY,
+}
+
+// --instances tb_ethernet.wb_slave:Tb_ethernetWb_slave --wave wishbone/ethmac/ethmac.fst
+module Tb_ethernetWb_slave : Wishbone {
+  in CLK_I : clock @posedge,
+  in RST_I : u1 = Wishbone.RST,
+  in ADR_I : u32 = Wishbone.ADR,
+  out DAT_I : u32 = Wishbone.DAT_I,
+  in DAT_O : u32 = Wishbone.DAT_O,
+  in WE_I : u1 = Wishbone.WE,
+  in STB_I : u1 = Wishbone.STB,
+  in CYC_I : u1 = Wishbone.CYC,
+  out ACK_O : u1 = Wishbone.ACK,
+  in SEL_I : u4 = Wishbone.SEL,
+  out ERR_O : u1 = Wishbone.ERR,
+  // out RTY_O : u1 = Wishbone.RTY,
+}
+
+// --instances tb_ethernet:Tb_ethernetEthSlWb --wave wishbone/ethmac/ethmac.fst
+module Tb_ethernetEthSlWb : Wishbone {
+  in wb_clk : clock @posedge,
+  in wb_rst : u1 = Wishbone.RST,
+  in eth_sl_wb_adr_i : u32 = Wishbone.ADR,
+  out eth_sl_wb_dat_i : u32 = Wishbone.DAT_I,
+  in eth_sl_wb_dat_o : u32 = Wishbone.DAT_O,
+  in eth_sl_wb_we_i : u1 = Wishbone.WE,
+  in eth_sl_wb_stb_i : u1 = Wishbone.STB,
+  in eth_sl_wb_cyc_i : u1 = Wishbone.CYC,
+  out eth_sl_wb_ack_o : u1 = Wishbone.ACK,
+  in eth_sl_wb_sel_i : u4 = Wishbone.SEL,
+  out eth_sl_wb_err_o : u1 = Wishbone.ERR,
+}
+
+// --instances tb_ethernet:Tb_ethernetEthMaWb --wave wishbone/ethmac/ethmac.fst
+module Tb_ethernetEthMaWb : Wishbone {
+  in wb_clk : clock @posedge,
+  in wb_rst : u1 = Wishbone.RST,
+  in eth_ma_wb_adr_o : u32 = Wishbone.ADR,
+  out eth_ma_wb_dat_i : u32 = Wishbone.DAT_I,
+  in eth_ma_wb_dat_o : u32 = Wishbone.DAT_O,
+  in eth_ma_wb_we_o : u1 = Wishbone.WE,
+  in eth_ma_wb_stb_o : u1 = Wishbone.STB,
+  in eth_ma_wb_cyc_o : u1 = Wishbone.CYC,
+  out eth_ma_wb_ack_i : u1 = Wishbone.ACK,
+  in eth_ma_wb_sel_o : u4 = Wishbone.SEL,
+  out eth_ma_wb_err_i : u1 = Wishbone.ERR,
+}
+

examples/wishbone/wishbone.prot

@@ -14,6 +14,8 @@ interface Wishbone {
     in DAT_O: u32,
     // error from server
     out ERR: u1,
+    // request to retry from server
+    out RTY: u1,
     // mask for data in/out from client
     in SEL: u4,
     // indicates a valid transfer cycle from client

protocols/src/frontend/remap.rs

@@ -130,10 +130,9 @@ fn implement_remap(
                 .pins
                 .iter()
                 .zip(pin_syms.iter())
-                .map(|(field, sym)| {
+                .flat_map(|(field, sym)| {
                     let name = format!("{}.{}", orig_mod.name, field.name());
-                    let mapping = pin_to_remap[&name];
-                    (*sym, mapping)
+                    pin_to_remap.get(&name).map(|&mapping| (*sym, mapping))
                 })
                 .collect();