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Imperial College London
- London, UK
- in/clarkechong
Pinned Loading
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parthak314/RISCV-Team5
parthak314/RISCV-Team5 PublicRISC-V 32I CPU designed as part of the instruction set architecture (ISA) module for 2nd year EIE at Imperial College London.
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qichao-arlo-wang/hlp-dsl-assembler-simulator
qichao-arlo-wang/hlp-dsl-assembler-simulator PublicF# 1
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ruc_C_compiler
ruc_C_compiler PublicANSI C90 to RISC-V compiler as part of Imperial College London's EIE Instruction Set Architecture and Compilers (Y2) coursework.
C++
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Circuit-Breakers-Smart-Grid-2025
Circuit-Breakers-Smart-Grid-2025 PublicSmart grid energy management system as part of the Imperial EIE/EEE year 2 summer project. Frontend application, backend server, Raspberry Pi Pico SMPS firmware and ESP32 master-slave.
Python
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