[biosed]

Summary

• implement Ampere F2IP.U8 byte packing
• let task shaders read their own 0xb8 payload output
• emit point, line and triangle mesh topology with point-size support
• align raw-global lookup with the 8,192-entry host ABI: tagged 2 MiB hints, a per-invocation last-entry cache and a looped bounded fallback
• resolve LDG.64/LDG.128 once and issue one aligned vector load, explicitly requiring the complete vector to remain inside one pool
• retain byte-identical SPIR-V for the prior triangle inventory before the raw-global optimization

This PR is based on the public Switch 2 native foundation commit 96cc0e883c80117e51342c60facfae2f0e600b9a. The repository current main is a newer Android/Mac fork that does not contain that foundation, so this explicit base keeps the GPL translator delta small and reviewable.

Checks

• test_dmsh_ampere_mesh.py: 11/11 synthetic fixtures pass
• test_dmsh_raw_reuse.py: 3/3 hint/cache/loop/vector fixtures pass, including the vector-end guard
• all five real point-mesh keys translate and pass spirv-val --target-env vulkan1.3
• full 520-job optimized run: 520/520 translated; 520 raw plus 520 canonical modules pass Vulkan 1.3 validation
• canonical inventory: 20 task + 500 mesh, 0 translation/reflection failures, t_vk_mesh passed
• 109 changed raw modules shrink in aggregate from 52,145,000 to 40,927,928 bytes
• observed producer 4c7d6be5a7717c8d: raw SPIR-V 615,692 -> 476,064 bytes and integer helper calls 529 -> 166 versus the checked per-access fallback

M1 Pro hardware evidence

The pre-guard vector build ab421bce, chain 5ab967c9784e, ran the same guarded Link-house idle route with an image identical to baseline:

• original 514-module set on Mesa 7d7af71bba3: frame 40.18 ms, GPU 35.93 ms
• vector set on Mesa 9cc3e7c7497: frame 34.62 ms, GPU 30.54 ms
• improvement: 5.6 ms frame / 5.4 ms GPU, about 14% (~25 -> ~29 fps)
• producer shaderdb: maximum 117,643 instructions, p50 53,928; top spills 374, still 255 GPRs / 384 threads

Triangle lowering is byte-identical between the two Mesa commits, so the comparison is valid. The final d83d66ab guard was then confirmed on the same hardware route with an identical image at 35.13 ms frame / 31.02 ms GPU; its 12 recompiled producers had maximum 117,873 and p50 54,088 instructions, with 410 top spills. This is evidence for the bounded idle route, not Vulkan conformance or full playability.