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FPGA link to interface an eDVS with SpiNNaker

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FPGA eDVS - SpiNNaker connection User guide

Key 0 – RST
Key 1 is broken
Key 2 - Start

LEDG 1 – dumping packets for spinnaker
LEDG 2 – SpiNNaker ready
LEDG 0 – packet ready

LEDR 0 – transmitting to eDVS
LEDR 1 – receiving from eDVS

SW 1 send data to MATLAB

RS 232 send data to MATLAB

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FPGA link to interface an eDVS with SpiNNaker

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