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add note about DDRx memory DQ/DQS signals #5

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add note about DDRx memory DQ/DQS signals #5

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1 change: 1 addition & 0 deletions schematic-checklist.md
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Expand Up @@ -51,6 +51,7 @@ off as invalid.
* [ ] AC coupling caps on gigabit transceivers
* [ ] TX/RX paired correctly for UART, SPI, MGT, etc
* [ ] Differential pair polarity / pairing correct
* [ ] The DQS pairs of DDRx memory interfaces are routed to DQS pins that can be used for the corresponding DQ byte lanes
* [ ] Active high/low enable signal polarity correct
* [ ] I/O banking rules met on FPGAs etc

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