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0cdc270
feat: add trusted Embody adapter and official ICASSP paper build
appleweiping Sep 8, 2026
7a56f4b
fix: pin POSIX checkpoint ownership and snapshot release blobs
appleweiping Sep 8, 2026
04ee07c
fix: preserve canonical Morlet kernels across verified Linux runtime
appleweiping Sep 8, 2026
e982d69
feat: connect private-host training lifecycle and checkpoint observers
appleweiping Sep 8, 2026
7e7f4e8
docs: publish native editable figures and verified ICASSP draft
appleweiping Sep 8, 2026
aaadd88
feat: add verified frozen CLIP text feature adapter
appleweiping Sep 8, 2026
fefd966
feat: resume residual attempts with verified checkpoint copies
appleweiping Sep 8, 2026
3380bf1
Connect immutable prepared-data v2 to the verified host runtime
appleweiping Sep 8, 2026
9456c52
Freeze native attention fastpath after server inference requalification
appleweiping Sep 8, 2026
e3c73c0
Integrate capture-level validation with snapshot-bound training and r…
appleweiping Sep 8, 2026
ed9e75a
Add receipt-bound capture storage and verified full-width CUDA lifecy…
appleweiping Sep 8, 2026
1731e9a
Wire complete-capture validation into host and fix Windows storage id…
appleweiping Sep 8, 2026
db71a83
Keep capture-index fixtures canonical across Windows and Linux
appleweiping Sep 8, 2026
9f1d4a2
Connect completed base checkpoints to full capture validation
appleweiping Sep 8, 2026
363422a
Bind window caption provenance and fix CLIP chunk coverage
appleweiping Sep 8, 2026
16f4b51
Add verified cohort qualification and bounded descriptor cache
appleweiping Sep 8, 2026
b04a3a4
Integrate verified periodic descriptor caches into model execution
appleweiping Sep 8, 2026
14eca09
Fix canonical host admission and real command-intent bindings
appleweiping Sep 8, 2026
05f9372
Bind prepared descriptor lineage and strict CUDA UUID identity
appleweiping Sep 8, 2026
9a072e5
Integrate capture cache lineage and verified CUDA workspace release
appleweiping Sep 8, 2026
578f52f
Integrate complete capture cache and host qualification controller
appleweiping Sep 8, 2026
d6d8089
Integrate complete descriptor cache construction and cached residual …
appleweiping Sep 8, 2026
093cfc7
Implement PhaseSet V2 directional temporal coordination research APIs
appleweiping Sep 26, 2026
d984c72
Align PhaseSet V2 with supplied handoff splits and temporal contracts
appleweiping Sep 26, 2026
3a51ccf
Refresh tracked release manifest after handoff integration
appleweiping Sep 26, 2026
7d89315
Add halo convolution and actor history with native asset qualification
appleweiping Sep 26, 2026
d9e5866
Preserve continuous capture coordinates and actor-edge phase trajecto…
appleweiping Sep 26, 2026
97ba196
Record complete native input audit and prescore task eligibility
appleweiping Sep 26, 2026
2b2a4ba
Record source-bound continuous CUDA mechanism qualification
appleweiping Sep 26, 2026
db0c088
Add signed-vector training calibration and disk-backed capture responses
appleweiping Sep 27, 2026
f28180c
Connect full-capture artifacts to independent calibration populations
appleweiping Sep 27, 2026
303b59a
Add consistent shared-yaw whole-capture training inputs
appleweiping Sep 27, 2026
1bd5755
feat: bind full-capture temporal relations to human text and annotati…
appleweiping Sep 27, 2026
1e8999e
feat: assemble native parent timelines without compressing gaps
appleweiping Sep 27, 2026
65d68eb
ci: bound CPU thread pools and record backend diagnostics
appleweiping Sep 27, 2026
2139438
feat: index complete-parent galleries and variable human positives
appleweiping Sep 27, 2026
9f627aa
test: isolate portable CPU BF16 autocast replay from native backend
appleweiping Sep 27, 2026
1063ca4
feat: add complete-parent sampler and full-gallery gradient replay
appleweiping Sep 27, 2026
3dacca9
feat: add training-only MIME parent curriculum component
appleweiping Sep 27, 2026
4fcd0c5
feat: add complete-parent residual optimizer and resume host
appleweiping Sep 27, 2026
269efbf
feat: train registered bases on complete parent captures
appleweiping Sep 27, 2026
2b66e07
feat: preserve complete TMR VAE and training objective
appleweiping Sep 27, 2026
1b885b7
feat: implement complete-parent TMR-Set VAE and pinned language
appleweiping Sep 27, 2026
313d02a
feat: implement complete-parent WaMo stationary wavelet baseline
appleweiping Sep 27, 2026
43a291d
feat: implement original dyadic and full-parent MIME with trainable CLIP
appleweiping Sep 27, 2026
e76c4bd
fix: use strict extracted CLIP transformer API and actual component o…
appleweiping Sep 27, 2026
d26f8bd
feat: replay full-negative WaMo and trainable MIME parent gradients
appleweiping Sep 27, 2026
33ee158
feat: replay complete TMR VAE parent gradients with full batch negatives
appleweiping Sep 27, 2026
77eb87b
feat: train faithful literature baselines with complete parent resume…
appleweiping Sep 27, 2026
ffbaa24
Add fixed human language row cache for full-parent TMR and WaMo
appleweiping Sep 27, 2026
7a0f7c5
Add full-parent disk source with independent deterministic group yaw
appleweiping Sep 27, 2026
d4d5096
Connect frozen CLIP preparation rows to complete-parent hosts
appleweiping Sep 27, 2026
371170c
Add leased parent operation heartbeats and checkpoint retention
appleweiping Sep 27, 2026
144570e
feat: persist V2 study budgets and rooted restart accounting
appleweiping Sep 27, 2026
a34b665
Add owned-process study execution and user-selected ICMR target
appleweiping Sep 27, 2026
4484c9d
Document native CPU lifecycle proof and amended relation supervision
appleweiping Sep 27, 2026
c20ce88
feat: separate weak counterfactual loss and complete-parent counts
appleweiping Sep 27, 2026
479b57c
feat: qualify stage-isolated cached weak CLIP pools
appleweiping Sep 27, 2026
9ee2ec2
docs: record actual weak-caption and CLIP preparation
appleweiping Sep 27, 2026
2a2543b
docs: record native full-capture weak-supervision backward evidence
appleweiping Sep 27, 2026
6e63f5a
fix: preserve literature optimizer settings across parent resume
appleweiping Sep 27, 2026
3c150b4
fix: wire MIME parent curriculum into actual optimizer host
appleweiping Sep 27, 2026
041be38
Harden parent optimizer cursor failure evidence
appleweiping Sep 27, 2026
8739854
Refresh release manifest for cursor integrity fix
appleweiping Sep 27, 2026
1cf95e6
Guard pilot reservations against concurrent formal freeze
appleweiping Sep 28, 2026
86623f1
Guard pilot cost floor inside budget reservation
appleweiping Sep 28, 2026
42f3c03
Lock 40-parent 200-caption retrieval geometry
appleweiping Sep 28, 2026
2dcf12d
Refresh tracked release manifest for retrieval regression
appleweiping Sep 28, 2026
e9d76f8
Freeze V2 pretest decision rules and correct analysis units
appleweiping Sep 28, 2026
a5b884f
Add V2 paired parent inference arithmetic witness
appleweiping Sep 28, 2026
41b3d81
Assemble V2 paired statistics from frozen score census
appleweiping Sep 28, 2026
f79e380
Gate study attempts and formal freeze on bounded storage
appleweiping Sep 28, 2026
4515cc7
Add advisory V2 cumulative storage forecast
appleweiping Sep 28, 2026
99b6d29
Refresh release file manifest for storage forecast
appleweiping Sep 28, 2026
f2b7256
Add true mean-difference DCT physical control primitive
appleweiping Sep 28, 2026
3b3cb10
Wire true DCT relations into V2 retrieval seam
appleweiping Sep 28, 2026
894d2e2
Fit training-only A6 DCT energy floors with bounded census
appleweiping Sep 28, 2026
15452a6
Encode relation checkpoint identity as tensor state
appleweiping Sep 28, 2026
5506bec
Add receipt-bound no-Morlet A6 disk views
appleweiping Sep 28, 2026
ff52a55
Document A6 native source qualification
appleweiping Sep 28, 2026
deca131
Add PhaseSet V2 incidence-shuffle control
appleweiping Sep 28, 2026
0bf294d
Add PhaseSet V2 order-free temporal control
appleweiping Sep 28, 2026
ec3ac56
Add capacity-matched PhaseSet V2 pair-bag control
appleweiping Sep 28, 2026
2e8273d
Bind PhaseSet V2 mechanisms to registered parent runs
appleweiping Sep 28, 2026
3dcc8fd
Restore literature host compatibility with registered identities
appleweiping Sep 28, 2026
81e5772
Implement speed-only periodic A1 control with bound floors
appleweiping Sep 28, 2026
2099830
Preserve checkpoint identity error compatibility
appleweiping Sep 28, 2026
de80dc8
Implement phase-independent A7 generic local control
appleweiping Sep 28, 2026
d185321
Bind all nine V2 base qualification rows to parent hosts
appleweiping Sep 28, 2026
7e5138d
Add calibrated legacy PhaseSet score control
appleweiping Sep 28, 2026
914fcb6
Pool legacy PhaseSet tokens over complete captures
appleweiping Sep 28, 2026
07e783b
Add provisional whole-parent legacy and A9 scoring seam
appleweiping Sep 28, 2026
49e0f23
Bind legacy scalar floor receipts to whole-parent scorer
appleweiping Sep 28, 2026
b4c7584
Connect legacy full-parent scorers to typed host bindings
appleweiping Sep 28, 2026
5cacc74
Bind registered legacy controls to selected B2 parent host
appleweiping Sep 28, 2026
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10 changes: 9 additions & 1 deletion .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,12 @@ jobs:
verify:
name: Windows Python ${{ matrix.python }}
runs-on: windows-latest
# Freeze native CPU pools before Torch/NumPy import, as in server witnesses.
env:
OMP_NUM_THREADS: "1"
OPENBLAS_NUM_THREADS: "1"
MKL_NUM_THREADS: "1"
PYTHONHASHSEED: "0"
strategy:
fail-fast: false
matrix:
Expand Down Expand Up @@ -44,7 +50,9 @@ jobs:
- name: Lint
run: python -m ruff check src tests scripts
- name: Test
run: python -B -m pytest -p no:cacheprovider -q ${{ matrix.pytest_args }}
run: |
python -B -c "import torch; print({'torch': torch.__version__, 'cpu_capability': torch.backends.cpu.get_cpu_capability(), 'num_threads': torch.get_num_threads(), 'num_interop_threads': torch.get_num_interop_threads(), 'mkldnn_available': torch.backends.mkldnn.is_available(), 'mkldnn_enabled': torch.backends.mkldnn.enabled}); assert torch.get_num_threads() == 1"
python -B -m pytest -p no:cacheprovider -q ${{ matrix.pytest_args }}
- name: Build wheel
run: python -m pip wheel --no-deps --wheel-dir dist .
- name: Audit built wheel bytes
Expand Down
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,7 @@ paper/*.bbl
paper/*.blg
paper/*.log
paper/*.out
paper/.venue/
figures/*_preview.png

recommend paper/
Expand Down
28 changes: 28 additions & 0 deletions LICENSE_TMR.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
# TMR components attribution

The ACTOR-style components and objective in
`src/phaseset_core/tmr_components.py` are adapted from
[Mathux/TMR](https://github.com/Mathux/TMR/tree/6d74688730d15d43b0a755ce2b0e1f2d76138fc1).
No pretrained weights, datasets, or third-party paper PDFs are included.

MIT License

Copyright (c) 2023 Mathis Petrovich

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
125 changes: 123 additions & 2 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -37,9 +37,130 @@ multi-person skeleton sequence
an independently hashed 20-Hz formula bank after resampling. This is a
compatibility boundary, not a claim that the two kernel banks or full models
are bitwise identical. See the
[20-Hz rate contract](docs/PHASESET_20HZ_MORLET_CONTRACT.md).
[20-Hz rate contract](docs/PHASESET_20HZ_MORLET_CONTRACT.md) and
[canonical-byte portability policy](docs/MORLET_PORTABILITY.md).

## Current milestone
## PhaseSet-V2 research upgrade — 2026-09-26

The user-selected target is now [ACM ICMR 2027](docs/PHASESET_V2_ICMR_TARGET.md).

The subsequent [relation-supervision amendment](docs/PHASESET_V2_RELATION_SUPERVISION_AMENDMENT.md)
uses existing official human retrieval annotations and permits separately
disclosed weak machine supervision; no new human annotators are awaited.
Machine labels are not independent motion ground truth or human-challenge
success. The [separate weak-CF loss/backward seam](docs/PHASESET_V2_WEAK_CF_TRAINING_SEAM.md)
has passed 37 scoped server checks, and the
[cached training-only weak text pool](docs/PHASESET_V2_WEAK_CLIP_POOL.md) has passed
24 additional scoped checks. Actual generation, encoded weak text and private
provenance admission remain pending. Neither is a completed native training run.

A [complete-native-parent CPU profile](docs/PHASESET_V2_NATIVE_PROCESS_PROFILE.md)
has now passed through the production lifecycle and journal: both 512-D systems,
all 55 accepted windows and 10 official human rows, full-negative backward
replay, unchanged weights, zero optimizer/GPU use. This is not formal training,
GPU throughput or a paper retrieval result; formal stages remain **0/87**.
The venue amendment changes submission format, not the scientific matrix or
compute budget. The existing ICASSP manuscript is historical, not an ICMR-ready
paper or a submitted result.

The new [V2 amendment](docs/PHASESET_V2_AMENDMENT.md) introduces signed local
phase, time-varying actor–edge incidence, chronological capture readout, and
verified counterfactual coordination supervision. The
[87-stage matrix](configs/phaseset_v2_experiment_matrix.json) supersedes the
affected legacy 33-run plan. New modules are independent research APIs; the
production V2 training-host integration and converged literature reproductions
are not yet qualified.
The V2 A6 comparator now has a data-free, whole-capture relation seam that
forms actual `(a+b)/2` and `a-b` velocity signals *before* six-band DCT,
retaining their cross term. This is distinct from legacy system 03's separate
endpoint self-power control and is not an InterEdit reproduction. A6 requires
its own typed, training-population DCT-floor receipt. Five real training-only
floor populations and the [native source-binding qualification](docs/PHASESET_V2_A6_SOURCE_QUALIFICATION.md)
have private server receipts; future run-bound GPU, cost, and checkpoint
admission remains separate. Neither the source check nor its CPU tests
constitute an A6 training run.
The [A4 incidence-shuffle control](docs/PHASESET_V2_A4_INCIDENCE.md) preserves
physical pair packets, edge support and model capacity while deterministically
reassigning supported half-edge values at the actor-incidence node input. Its
shuffle is independent of private participant commitments. Software review
and tests do not count as formal A4 training or retrieval results.
The [A2 order-free control](docs/PHASESET_V2_A2_ORDER_FREE.md) replaces all
four learned temporal GRU paths with near-equal-capacity independent patch
MLPs and masked means while retaining the same physical phase input. It tests
the contribution of learned order, not the existence of physical phase.
The [A3 capacity-matched pair-bag control](docs/PHASESET_V2_A3_PAIR_BAG.md)
keeps the full head's active node and edge modules but pools relation packets
without assigning them to actor nodes. It is distinct from the legacy
topology-off pair-only diagnostic and has no reported retrieval result yet.
The [matrix-bound V2 mechanism factory](docs/PHASESET_V2_MECHANISM_FACTORY.md)
constructs the implemented main B2 and full/A1/A2/A3/A4/A5/A6/A7/A8 host paths
with registered seeds, predecessor/terminal and source bindings. The A7
focused registered-server CPU qualification passed 42 tests with one
CUDA-only skip; it grants no pilot or
formal launch, and A9, fold hosts and Inter-X remain held. A7 is a
[generic local relation control](docs/PHASESET_V2_A7_GENERIC_LOCAL.md): its
scores ignore phase features, while its shared input transport still incurs
phase-cache preparation cost.
[TMR-Set](docs/TMR_SET_ADAPTATION.md) now implements the
complete original VAE objectives with disclosed full-parent group adaptation;
its pinned frozen language loader is not a substitute for native learning.
[WaMo-Set](docs/WAMO_SET_ADAPTATION.md) implements learnable stationary analysis
and inverse wavelets, both reconstruction branches and original/shuffled-frame
ordering, with explicit full-parent group adaptation and unpublished-detail
choices. Its software qualification is not converged baseline training.
[MIME](docs/MIME_SET_ADAPTATION.md) keeps separate role-aware original dyadic
and shared complete-parent group APIs, full-time bidirectional co-attention,
and a genuinely trainable pinned CLIP text tower. Group XYZ/long-text adapters
are disclosed; equation/software checks are not original-task convergence.
Their [full-negative parent backward seam](docs/PHASESET_V2_LITERATURE_PARENT_TRAINING.md)
replays one complete capture graph at a time without dropping original WaMo
auxiliary objectives or freezing MIME text. Dense-gradient software oracles
are not native optimizer, profile, checkpoint-host or convergence evidence.
The separate [TMR VAE parent backward seam](docs/PHASESET_V2_TMR_PARENT_TRAINING.md)
preserves the original stochastic order, both full-track reconstructions,
all four KL terms, latent alignment and filtered full-batch negatives; it does
not route TMR through a generic contrastive-only objective.
The [literature optimizer host](docs/PHASESET_V2_LITERATURE_PARENT_HOST.md)
shares the full-parent AdamW, validation selection and checkpoint/resume loop,
while keeping each baseline's original objective. Analytic optimizer/resume
checks and native dense-gradient replay are distinct from a native training
pilot or converged baseline result.
The [fixed TMR/WaMo language-row cache](docs/PHASESET_V2_FROZEN_LANGUAGE_ROWS.md)
retains every human caption occurrence and content token, reusing only frozen
features; MIME still trains its own genuine CLIP tower.
The [development disk source](docs/PHASESET_V2_PARENT_DISK_SOURCE.md) streams
complete body/phase timelines and uses source/seed/epoch group yaw independent
of model RNG. Caption eligibility and run-specific floors remain explicit
private inputs. The [frozen human CLIP row source](docs/PHASESET_V2_FROZEN_CLIP_ROWS.md)
connects base/V2 human-only text using exact cached preparation rows with a
distinct derived receipt, not a new encoder invocation. The genuine verified-CF
pool and production admission remain pending.
The [parent operation monitor](docs/PHASESET_V2_PARENT_OPERATION_MONITOR.md)
holds a process-released lease, emits independent long-operation heartbeats and
supports explicit recent/best checkpoint retention without deleting predecessor
or historical evidence. It does not grant formal starts or global compute budget.
The [persistent study budget](docs/PHASESET_V2_STUDY_BUDGET.md) preserves actual
historical GPU charges, pending wall-time envelopes, fixed pilot allocations,
and rooted formal predecessors. Bookkeeping alone does not qualify process
execution or scientific admission.
The [Linux process controller](docs/PHASESET_V2_STUDY_PROCESS.md) connects
reservations to owned child sessions, verified exit and actual wall-time charges.
Its 23 focused tests ran on the registered Linux server with actual stdlib
children, not native training. Native GPU integration and scientific admission
still need their own evidence.

[Server mechanism verification](docs/PHASESET_V2_MECHANISM_VERIFICATION.md)
records 117 focused CPU tests and one full-width CUDA forward/backward witness.
There are still **0/87 formal V2 stages** and no native-data retrieval result.
Approved main-data and licensed body-model assets have been obtained privately,
and the handoff fold assignments have been recovered. Complete development-parent
preprocessing and five training-only physical calibrations have closed private
receipts. Run-specific admission, faithful baseline training, resource profiling,
and real human relational verification still require actual execution evidence.
The descriptions and score equation below document the preserved V1 core,
not completed V2 experiments or a submission-ready paper.

## Preserved V1 milestone

This source snapshot declares `v0.2.1`, the portable-verification patch for the
stable data-free multi-person core and execution-contract milestone. It is a
Expand Down
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