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1. RISC-V-System-On-Chip RISC-V-System-On-Chip Public

   RISC-V System-on-Chip implementation featuring FPGA deployment on Xilinx Vivado and ASIC RTL-to-GDSII backend physical design flow.

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2. liberty-timing-analyzer liberty-timing-analyzer Public

   Parser and interactive visualizer for Liberty (.lib) STA timing files — verified across Sky130, NanGate45, GF180MCU, and IHP SG13G2

   Python