Pinned Loading

1. pipelined-5stage-risc-core pipelined-5stage-risc-core Public

   Synthesizable 5-stage pipelined Harvard RISC processor in VHDL with hazard forwarding, branch prediction, hardware interrupts, and exception handling.

   VHDL

2. sram-puf-ice40 sram-puf-ice40 Public

   End-to-end SRAM Physical Unclonable Function (PUF) implementation on a Lattice iCE40 FPGA with statistical characterization and a Reed-Solomon Fuzzy Extractor for cryptographic key derivation.

   Verilog 1

3. aes-128 aes-128 Public

   Compact Verilog AES-128 core on Lattice iCE40 with Cocotb testbench, 1.5 Mbps UART, and fully open-source EDA flow (113 MHz, 27% LCs).

   Verilog

4. fpgahammer-ice40 fpgahammer-ice40 Public

   Ring-oscillator voltage glitching and Differential Fault Analysis (DFA) on Verilog AES-128 using a Lattice iCE40HX8K FPGA.

   Verilog 1

5. r2sdf-fft r2sdf-fft Public

   Radix-2 SDF streaming N-point DIF Fixed-Point FFT core, a corresponding Bit-accurate python model, and OpenLane ASIC implementation in SkyWater 130nm.

   Verilog

6. federated-learning-on-edge-stm32u5 federated-learning-on-edge-stm32u5 Public

   Distributed on-device FedAvg across STM32U585 microcontrollers: trains a lightweight CNN head for Human Activity Recognition, synced over Wi-Fi using Azure RTOS NetX Duo.

   C