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ahmedbadwy77/README.md

Ahmed Badwy Mohamed

Digital IC Design · RTL & Design Verification

Cairo University — ECE '28  ·  Cairo, Egypt

LinkedIn Email

👤 About

I'm an Electronics & Communications Engineering student at Cairo University, focused on digital IC design.

Hardware has to be right — not approximately right. I like the craft of it: clean RTL, verified rather than assumed, then carried through synthesis and timing.

I'm deepening that practice through structured digital IC design training, and looking for a team where rigour matters as much as it does to me.

Open to: Digital IC · RTL design · Design Verification internships.

 Volibear — the Relentless Storm

🎯 Focus

Area Scope
RTL Design Verilog · SystemVerilog · VHDL · FSMs · pipelining · fixed-point datapaths
Verification Self-checking testbenches · SVA · code & functional coverage · equivalence vs golden models
FPGA & ASIC Flows Synthesis · STA · Lint/CDC/RDC · DFT · formal equivalence · GLS · physical design to GDS
Hardware-Aware Software RISC-V RV64GC / RV64GCV vector programming · C++17
Embedded AVR · ESP32 · Raspberry Pi · I2C / GPIO / timers / ADC

🛠️ Toolchain

HDL & Digital Design Verilog SystemVerilog VHDL

Verification & Implementation SVA Coverage STA CDC Formal GLS

Programming C++ Python TCL

EDA ModelSim · Vivado · Design Compiler · SpyGlass · Formality · Cadence Virtuoso

📊 GitHub

Followers Last commit

📫 Contact

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  1. Canny-Edge-RISCV Canny-Edge-RISCV Public

    High-performance Canny Edge Detection pipeline for RISC-V (RV64GCV), optimized with Vector Intrinsics (RVV) and verified with GoogleTest.

    C++ 1

  2. sscs26-cnn-accelerator sscs26-cnn-accelerator Public

    Streaming N-by-N CNN convolution accelerator on Xilinx Zynq-7020 – 50 LUT / 9 DSP / 0 BRAM / 464 MHz at 2.155 ns / FOM 0.01550 – IEEE SSCS Egypt 2026 Student Design Competition (Team FlipFlopers, C…

    Verilog

  3. Low-Power-Multi-Clock-Digital-Communication-System Low-Power-Multi-Clock-Digital-Communication-System Public

    Full RTL-to-GDSII ASIC implementation of a 100MHz low-power multi-clock digital communication SoC in TSMC 130nm, featuring robust CDC, Integrated Clock Gating (ICG), and complete physical sign-off.

    Verilog