[AIE2P] Implement sparse fifo_ld + sparse extract/concat/insert

[matteius]

Summary

Two commits filling in the AIE2P sparse-vector toolchain gap:

1. [AIE2P][Headers] Implement sparse extract/concat/insert via field access — header-only.
   Defines the AIE2P-larger sparse vector types (v512uint4_sparse, v256uint8_sparse, v128uint16_sparse, v512int4_sparse, v256int8_sparse, v128int16_sparse) as composite structs holding lo + hi halves of the AIEv2-sized (640-bit) sparse vectors. Mirrors the v128bfp16ebs* pattern at aiebase_typedefs.h:563-576.
   Implements the existing extract_sparse_data / extract_v* / concat / set_v* / insert forward-declared surface using struct field access (return v.data;) instead of __builtin_aiev2_ext_qx (which is supplied by Vitis Chess but not by upstream Peano).
   Removes the conflicting empty-stub struct v256int8_sparse {}; family from aie2p_aie_api_compat.h.
   No clang/LLVM rebuild required.

2. [AIE2P] Implement v128int8_sparse fifo_ld_pop L3-L5 backend chain — full backend addition.
   Adds the missing 640-bit sparse FIFO load intrinsic so v128int8_sparse fifo_ld_pop lowers to the existing silicon ops vlda.pop.640 / vldb.pop.640 (already wired into VLD_POP_640_normal_pop_pseudo at AIE2PMultiSlotPseudoInstrInfo.td:109).
   Layers added (mirrors the BFP16 multi-output shape):

   • L3 — clang builtin __builtin_aie2p_fifo_ld_pop_640_unaligned_sparse with sig vv*&V32i&i&V64c&V16c& (ptr-ref, fifo-state, pos, data-out, sparsity-mask-out).
   • L4 — LLVM IR intrinsic int_aie2p_fifo_ld_pop_640_unaligned_sparse returning the 5-tuple [anyptr, v32i32, i32, v64i8, v16i8].
   • L5 — selectVLD_FIFO_POP_640_SPARSE: allocates a virtual mQXsa (640-bit) reg, builds VLD_POP_640_normal_pop_pseudo, splits the 640-bit dst back into data (sub_sparse_x) + mask (sub_sparse_q) via a new buildAndConstrainSparseFifoLoadCopies helper (mirrors buildAndConstrainFifoLoadCopies / sub_bfp16_*). Registered as memory-touching in getTgtMemIntrinsic and as a FIFO-reg user in isUsedAsFifoRegInIntrinsic + getUnderlyingObjectAIEIntrinsic.
   • L2 — FIFO_LD_SPARSE / FIFO_LD_SPARSE_WIDE macros in aie2p_ldst.h (mirrors FIFO_LD_BFP16*); the wide form composes two narrow pops into v256int8_sparse via the composite-struct helpers from commit 1.
   • typedef — adds v16char (16-byte char vector) to aiebase_typedefs.h to match the V16c builtin signature for the mask out-ref.

Net diff: 12 files, 468 insertions(+), 9 deletions(-).

Motivation

Compiling AIE2P kernels that consume aie::sparse_vector_input_buffer_stream<int8, 256>::pop against upstream Peano produced four undefined symbols. Two were closable with header-only fixes (commit 1). The remaining two (fifo_ld_pop, fifo_ld_fill on v256int8_sparse_unaligned) require silicon-load semantics — i.e. the clang builtin → LLVM intrinsic → SelectionDAG patterns mapping to the existing VLDA_POP_640_* silicon ops (commit 2).

Symbol-count progression on the same microtest:

• baseline: {fifo_ld_pop, fifo_ld_fill, extract_v128int8_sparse, extract_sparse_data, __muldi3} (5)
• after commit 1: {fifo_ld_pop, fifo_ld_fill, __muldi3} (3)
• after commit 2: {__muldi3} (1, libgcc)

Test plan

• Tier 1: test_sparse_intrinsic.ll lowers via llc to vldb.pop.640 cleanly; test_sparse_builtin.cc emits @llvm.aie2p.fifo.ld.pop.640.unaligned.sparse in clang -emit-llvm output; test_v128int8_narrow.cc compiles to a single vldb.pop.640 instruction.
• Tier 2: existing microtest passthrough_decompress.cc compiled with the new toolchain links with zero sparse undefined symbols; .o contains two vldb.pop.640 instructions (one per half of v256int8_sparse).
• Tier 4 (silicon): not yet run — opening as draft for design review while we get hardware time. Will promote out of draft once a Strix dev kit confirms the lowered pop produces correct data + mask values.

Marked draft because of the silicon gap. Happy to split commits, restructure, or change naming if vldb vs vlda convention or the sub_sparse_x / sub_sparse_q sub-register names diverge from upstream preferences.

[konstantinschwarz]

hi @matteius, thanks a lot for this contribution!

I didn't go through all details yet, but one observation upfront: could you please add tests for both the frontend lowering to IR (should go to clang/test/CodeGen/aie/aie2p), as well as instruction selection tests (in llvm/test/CodeGen/AIE/aie2p/GlobalISel)?