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New outputs: cut list and connector pinouts as Markdown - #3
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Pin ranges, bare connector names, sets that start or end with a cable, wires named by colour code, == mates, loops, pin colours, and duplicate keys, all read the way the hailey-v1 fork reads them. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
ferrule [--prepend FILE]... [--format svg,png] [--output-dir DIR] LOOM.yml writes an SVG that follows the viewer's theme and a dark PNG. Inter is measured with HarfBuzz, so kerning counts, and subset into each SVG, so no viewer falls back to another font. resvg gets the same faces as TTF. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Node won't strip types under node_modules, so a git install runs prepare and gets compiled JavaScript. Dependencies are pinned exactly: a consumer's lockfile resolves them from these ranges, and output bytes depend on them. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
TWIN.: [1, 2] is both cores of one new cable, not two cables. The parity check now compares instance numbers too, which is what would have caught it. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
- Full Inter faces from inter-ui, so Ω and → draw instead of a box. - Black cores are dark grey on the dark theme, so they don't look hollow; mates are a chain of dots, which no wire is drawn as. - Autogenerated connectors are titled by their template. - Subtitles wrap inside the card; notes rejoin hand-wrapped lines into paragraphs and may widen a card to its limit. - Tags sit on their wire; an unterminated core ends in a cap; colour chips have an outline so white ones show on a white card. - Wider spacing between parallel wires, and a sheet wider than 2.2:1 is wrapped into rows. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
- A mated pair is laid out as one node, so a wrap can't split it. - Only a sheet wider than 3:1 wraps: wrapping sends wires round the edge. - Notes join only a lowercase continuation; other line breaks are kept. - A loop with wires on both sides is a bracket inside the card. - Repeated parts are titled TEMPLATE · n; white cores are pale grey on the light theme; chip outlines are darker. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Missed from the review fix that switched to them. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
ELK's wrap cut through multi-core cables in every loom it touched, and the review rated those ribbons worse than a wide sheet. A part drawn once is titled by its template alone. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
- Reject a loop on a pin the connector lacks, and more pin labels than pincount, rather than drawing them wrong or dropping labels. - One rule picks a black or white core's casing, for wires and swatches. - The parity check passes the fork's errors through. - The README says what the parity check does and doesn't compare. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Build to parity: render all ten Hailey looms
`--format md` adds <loom>.md beside the diagrams: one row per core with its size, length and both ends, joined up across connection sets, and a table for each connector listing every pin, its wire and where that wire goes. GitHub renders both on a phone, where a wide diagram is hard to follow pin by pin. Hailey #155 step 5. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
A number after a cable in a pinout now always means a core: single cores read `RUN · 1 (BK)` and multi-core cables `LOOM core 1 (RD)`. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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Step 5 of XDGFX/hailey#155. Tagged
v0.2.0at b43b51c, which Hailey pins.--format mdwrites<loom>.mdwith two sections:svg,png), somdis opt-in. Asking formdalone skips layout.sheet.tsexportsfmtanddisplayNameso the tables name parts the same way the diagram does.Note on base: #2 was merged into
worktree-155-layout-spikeafter #1 had already merged, so the parity work never reachedmain. This branch starts from that merge (acdc3c0), so merging it brings #2 ontomaintoo.Part of XDGFX/hailey#155. The issue stays open, because step 6 (plumbing) remains.
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