Add Zbs single-bit operations implementation (RV32, SystemVerilog)

[jeff-7]

Implements RV32 Zbs single-bit operations:

• bclr / bclri
• bset / bseti
• binv / binvi
• bext / bexti

Design follows abstract ALU pattern:

• Module remains purely functional
• R/I distinction handled in decoder
• Uses SystemVerilog style (logic, always_comb)

[github-actions]

🔧 DE1-SoC Synthesis Report Summary Diff

📊 Fitter Summary (.fit.summary)

No baseline available from main branch

View PR synthesis results

Fitter Status : Successful - Tue Mar  3 06:33:05 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : utoss-risc-v
Top-level Entity Name : top
Family : Cyclone V
Device : 5CSEMA5F31C6
Timing Models : Final
Logic utilization (in ALMs) : 1,448 / 32,070 ( 5 % )
Total registers : 1255
Total pins : 15 / 457 ( 3 % )
Total virtual pins : 0
Total block memory bits : 16,384 / 4,065,280 ( < 1 % )
Total RAM Blocks : 4 / 397 ( 1 % )
Total DSP Blocks : 0 / 87 ( 0 % )
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )

⏱️ Timing Analysis Summary (.sta.summary)

No baseline available from main branch

View PR synthesis results

------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------

Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
Slack : 5.227
TNS   : 0.000

Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.363
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.868
TNS   : 0.000

Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
Slack : 5.398
TNS   : 0.000

Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.269
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.822
TNS   : 0.000

Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
Slack : 10.938
TNS   : 0.000

Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.182
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.787
TNS   : 0.000

Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
Slack : 11.838
TNS   : 0.000

Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
Slack : 0.171
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.780
TNS   : 0.000

------------------------------------------------------------

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Comparing synthesis results from main branch vs. this PR

[TheDeepestSpace]

Thanks for the PR! Let us merge #190 first, so that you can use the b_alu_control_t from it

[TheDeepestSpace]

for the documentation here I would just specify the section of the specification that corresponds to Zbs extension

[TheDeepestSpace]

Suggested change

	input logic [31:0] reg1 // rs1 operand
	, input logic [31:0] reg2 // rs2 or immediate (bit index source)
	input data_t reg1 // rs1 operand
	, input data_t reg2 // rs2 or immediate (bit index source)

I think we can use data_t here, let's check if that works for consistency