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…STAR, WIDTHTRUNC, port widths
…LENAME, IMPORTSTAR, WIDTHTRUNC, and a write-enable line from utoss_riscv.sv
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i think this got deleted by accident?
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| `timescale 1ns/1ps | ||
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i dont think i ever seen timescale being put in regular verilog files, is that a thing? i thought these we only relevant for testbenches
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| if (write_enable[0]) M[address[11:2]][7:0] <= write_data[7:0]; | ||
| if (write_enable[1]) M[address[11:2]][15:8] <= write_data[15:8]; | ||
| if (write_enable[2]) M[address[11:2]][23:16] <= write_data[23:16]; | ||
| if (write_enable[3]) M[address[11:2]][31:24] <= write_data[31:24]; |
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i think we can derive this value 11 from SIZE using $clog2(SIZE); can do localparam SIZE_W = $clog2(SIZE); and then use that in address subscript
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| /* verilator lint_off LATCH */ | ||
| /* verilator lint_off COMBDLY */ |
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I think we should fix this as part of this PR
| zba uut(.reg1(reg1) | ||
| , .reg2(reg2) | ||
| , .inst(inst) | ||
| , .funct3(3'b000) //these were missing |
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Suggested change
| , .funct3(3'b000) //these were missing | |
| , .funct3(3'b000) |
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all 5 changes seem to be present in this one