A from-scratch SystemVerilog behavioral model of the Xilinx RAMB18E1 7-Series block RAM primitive — implementing SDP mode, configurable read/write port widths (1–36 bits), parity handling, output latch/register pipeline stages, synchronous reset (RSTRAM/RSTREG) behavior, built by reverse-engineering UG953 and UG473 documentation alongside the official Xilinx Unisim simulation source.