An eight-port 100 Mbps Ethernet switch chip for the ECOS 2610 shuttle. It has no core: it forwards from the moment reset is released, and an SPI host can manage it when there is one.
Assembled by xirang from three blocks of the IP library, with no RTL of its own: eswitch, eight ports with 16 learned addresses and port isolation; spis, an SPI slave that masters the on-chip bus; gpio, six pins.
The board wiring, the chip tests and the limits are in docs/流片说明.md; the tape-out report is generated from that file.
$ python3 sw/switch.py --ftdi ftdi://ftdi:232h/1 boot # ageing counted in real seconds
$ python3 sw/switch.py --spidev 0.0 table # learned addresses and their ports
$ python3 sw/switch.py --spidev 0.0 counters # received, sent and dropped frames per port
$ python3 sw/switch.py --spidev 0.0 isolate 0-3,4-7 # two broadcast domains
$ python3 sw/switch.py --spidev 0.0 mdio 1 2 # read register 2 of the PHY at address 1sw/spis.py is the SPI protocol and sw/switch.py the register map and the operations. The chip tests drive the chip through these same two files.
$ ran test to2610-switch # the chip tests, on the Verilog file that goes to the shuttle
$ ran asic to2610-switch # to2610_switch.v, ecc at 50 MHz, report.json
$ ran asic to2610-switch --no-run # only the Verilog file and ecc.toml任选其一：
SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0
除非另行说明，你提交的贡献按上述三者同时授权，不附加其他条件。