Symmetric multiprocessor reference SoC: two cores sharing one memory.
Part of the Tape-Out IP library: Bluespec IP over the
bus-neutral contracts in hwcore, assembled by
xirang. Maturity runs planned -> simulated ->
fpga-proven -> asic-ready -> silicon-proven.
Assembled and tested end to end in CI; the badge stays at planned while the assembler is being reworked.
| Part | Repository | Configuration |
|---|---|---|
| cores | rvcore ×2 |
RV32IM, machine mode only |
| memory | sram |
1024 words (4 KiB) at 0x8000_0000, shared |
| interrupts | aclint · plic |
two harts · 8 sources, one context per core |
| inter-core | mbox |
mailboxes and 32 spinlocks |
| console | uart |
at 0x1000_1000 |
The four ports of the two cores share one switch, round-robin. There are no caches, so the memory is coherent by construction; rvcore has no atomic instructions, so mutual exclusion goes through mbox's spinlocks.
任选其一：
SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0
除非另行说明，你提交的贡献按上述三者同时授权，不附加其他条件。