Reference SoC for Linux with an MMU: a supervisor-capable core with Sv32, first level caches and a PLIC. Formerly soc-linux; the no-MMU line is soc-mcu.
Part of the Tape-Out IP library: Bluespec IP over the
bus-neutral contracts in hwcore, assembled by
xirang. Maturity runs planned -> simulated ->
fpga-proven -> asic-ready -> silicon-proven.
Assembled and tested end to end in CI; the badge stays at planned while the assembler is being reworked. It does not boot Linux yet; the target is ordinary Linux and the common distributions.
| Part | Repository | Configuration |
|---|---|---|
| core | rvcore |
RV32IM with supervisor mode and the Sv32 MMU |
| caches | cache ×2 |
instruction and data, 8 lines of 4 words, direct mapped, write through |
| memory | sram |
1024 words (4 KiB) at 0x8000_0000 |
| interrupts | aclint · plic |
one hart with supervisor software interrupts · 8 sources, 2 contexts |
| console | uart |
at 0x1000_1000 |
Fetch and load/store each go through their own cache, and the caches' lower ports share the switch. All four interrupt lines of the core are wired: machine software and timer from the CLINT, external from the PLIC, and the supervisor software edge. What Linux still needs: far more memory than 4 KiB, and the A extension, which rvcore does not have.
任选其一：
SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0
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