Microcontroller reference SoC: one core, on-chip memory, the common peripherals. No MMU; the Linux target on this line is no-MMU Linux. The MMU line is soc-mpu.
Part of the Tape-Out IP library: Bluespec IP over the
bus-neutral contracts in hwcore, assembled by
xirang. Maturity runs planned -> simulated ->
fpga-proven -> asic-ready -> silicon-proven.
Assembled and tested end to end in CI; the badge stays at planned while the assembler is being reworked.
| Part | Repository | Configuration |
|---|---|---|
| core | rvcore |
RV32IM, machine mode only, no MMU |
| memory | sram |
256 words (1 KiB) at 0x8000_0000 |
| timer and software interrupt | aclint |
one hart |
| peripherals | gpio ×2 · uart ×2 · timer · pwm · wdt · spi · i2c · rtc · pinmux |
at 0x1000_xxxx |
The core's two ports and an external APB4 port share one switch, round-robin among the on-chip managers. There is no interrupt controller: only the CLINT's software and timer interrupts reach the core, and the peripherals' interrupt lines come out as the top-level irqs vector.
任选其一：
SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0
除非另行说明，你提交的贡献按上述三者同时授权，不附加其他条件。