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RISC-V Processor

This project implements a RISC-V processor based on the RV32I instruction set architecture (ISA). It includes essential components such as instruction decoding, execution, memory access, and write-back stages. The goal is to create a functional and extensible RISC-V core capable of executing fundamental operations while allowing future enhancements.

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📌 Variant & Specifications

• Architecture: RISC-V 32-bit (RV32I)
• Instruction Set: Base Integer Instruction Set (I-type, R-type, S-type, B-type, U-type, J-type)
• Pipeline: Single-Cycle
• Registers: 32 General-Purpose Registers

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📁 File Structure

/project-root
│── Decode/               # Decode stage
│   ├── Decode.v          # Top-level decode module
│   ├── Decode_tb.v       # Testbench file
│   ├── Decode.vvp        # Compiled Simulation file
│   ├── Decode.vcd        # Waveform output file
│   ├── submodules/       # Supporting modules for Decode (similar structure)
│── Execute/              # Execute stage
│── Memory/               # Memory access stage
│── WriteBack/            # Write-back stage
│── Pipelined.v           # Top-level integration module
│── Pipelined_tb.v        
│── Pipelined.vcd         
│── Pipelined.vvp         
│── data.hex              # Data Memory Hex files
│── instructions.hex      # Instruction Memory Hex files

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🚀 How to Run

1️⃣ Install Dependencies

Before running the simulation, install Icarus Verilog (iverilog):

• Installation Guide (All OS)
• Windows Installation

2️⃣ Clone the Repository

git clone https://github.com/TanmayBansode/riscv
cd riscv

3️⃣ Navigate to the Desired Module

cd Decode

📌 Naming Conventions Used in the Project

File Type	Naming Convention
Design File	Module.v
Testbench	Module_tb.v
Compiled Simulation	Module.vvp
Waveform Output	Module.vcd

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🔧 Compilation & Simulation

✅ Option 1: Using veri (One-Command Execution)

If you have veri installed, you can compile and run the simulation with a single command:

veri Decode.v

📌 Option 2: Using iverilog (Manual Compilation)

Step 1: Compile the Design & Testbench

iverilog -o Decode.vvp Decode.v Decode_tb.v

Step 2: Run the Simulation

vvp Decode.vvp

Step 3: View the Waveform in GTKWave

gtkwave Decode.vcd

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🛠️ Technologies Used

• Languages: Verilog
• Tools & Simulators:
  • Compilation: Icarus Verilog (iverilog)
  • Simulation: GTKWave

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📌 Future Improvements

1. Implementing Hazard Detection & Forwarding to handle data and control hazards efficiently.
2. Building a Tool for Converting Assembly to Binary for easy instruction encoding.
3. Optimizing the Testing Process using UVM + SystemVerilog to improve verification coverage.
4. Adding Hierarchical Cache Levels (Data & Instruction Caches) to enhance memory performance.

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📚 References

• 📖 RISC-V Official ISA Manual
• 📕 Patterson & Hennessy’s Computer Organization & Design (RISC-V Edition)

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