Note on Academic Integrity: The following projects are based on advanced lab exercises completed at the University of Applied Sciences Bremen. To respect the intellectual property of Prof. Dr.-Ing. Stefan Wolter and the university's academic policies, the original assignment PDFs and restricted source files (such as professor-provided VHDL RTL) are not included in this repository.
All code presented here represents my own original implementation of verification environments, testbenches, and SystemVerilog Assertions (SVA) used to achieve 100% functional and code coverage, using the basic framework provided as part of the course.
To replicate these results, the following environment is required:
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Xilinx Vivado/ISE: Used primarily for the underlying hardware libraries and initial design synthesis.
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OVL (Open Verification Library): Utilized for standard checker instantiations to ensure design protocol compliance.
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Focus: Protocol verification of a VHDL-based synchronous FIFO.
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Task: Integrated an OVL FIFO Checker to monitor for data integrity, overflow, and underflow.
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Highlight: Developed a complete simulation script (.do file) to automate the compilation of VHDL and SystemVerilog files into a unified work library.
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Focus: Verifying non-binary counter transitions and asynchronous resets.
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Task: Authored Immediate Assertions for asynchronous reset timing and Concurrent Assertions to ensure the dout followed the 16-word Gray code sequence.
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Highlight: Used the Assertion Thread Viewer (ATV) to debug overlapping timing requirements for the enable control.
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Focus: Black-box verification of a complex serial transmitter.
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Task: Verified the 18-bit pilot-tone preamble and the specific FM0 "biphase space" encoding rules (where a '0' requires a mid-bit transition).
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Highlight: Managed state-machine verification for a one-hot encoded FSM with six distinct states.
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Focus: Transitioning to structured, object-oriented verification.
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Task: Built a self-checking environment for an IEEE-754 FPU including a Stimulus Generator, Driver, Monitor, and Comparator.
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Highlight: Implemented DPI-C (Direct Programming Interface) to link a Golden Model written in C to the SystemVerilog testbench for result comparison.
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Focus: Automating test generation for edge-case detection.
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Task: Developed SystemVerilog Constraints to specifically target "corner cases" in floating-point math, such as NaN (Not a Number), Infinity, and Zero.
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Highlight: Used randcase to weight the distribution of operands, ensuring the simulator hit difficult-to-reach logic in the FPU.
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Focus: Closing the "verification loop" to ensure no feature went untested.
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Task: Defined Covergroups and Coverpoints for all operations and rounding modes.
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Highlight: Achieved 100% merged code and functional coverage by mapping simulation results to a formal Verification Plan (.xml) using the Questa Verification Tracker
Completing this series of six intensive labs provided a comprehensive mastery of the Hardware Verification Life Cycle. Through this curriculum, I transitioned from basic signal checking to managing complex, production-grade verification environments.
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Advanced Assertion-Based Verification (ABV): I learned to move beyond simple waveforms by implementing SystemVerilog Assertions (SVA) and OVL Checkers to catch protocol violations in real-time.
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Object-Oriented Verification (OOV): By building a class-based testbench for a Floating Point Unit, I mastered the separation of concerns between Stimulus Generation, Driving, and Monitoring.
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Golden Model Integration: I gained experience in Mixed-Language Verification by using the DPI-C interface to verify RTL behavior against a C-based reference model, a critical skill for verifying complex algorithms.
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Automation & Toolchain Proficiency: I developed a "script-first" workflow using Tcl/Do scripts to automate repetitive compilation and simulation tasks in Questa, ensuring a reproducible and efficient verification environment