Final-year B.Tech ECE student at Amrita Vishwa Vidyapeetham, focused on analog IC design, sensor interfaces, and CMOS circuit verification. I use Cadence Virtuoso, Spectre, LTspice, and Python to move from topology selection and hand analysis to transistor-level characterization, signal-chain studies, trade-off analysis, and reproducible technical documentation.
I am interested in analog / mixed-signal IC design roles, semiconductor internships, and graduate research in microelectronics.
| Project | What I designed and verified | Status |
|---|---|---|
| 45 nm StrongARM Dynamic Comparator | 5 GHz dynamic comparator with static decision capture; 55.73 ps nominal (t_{90}), 13.98 fJ/comparison, mismatch/noise analysis, and a 45-point deterministic PVT campaign | Comparator + capture complete; full EOM integration ongoing |
| Positive-Feedback OTA Ring VCO | Architecture screening, tail-current tuning, diode-PMOS common-mode restoration, and practical NMOS mirror trade-offs in GPDK090 | Ongoing publication-oriented schematic research |
| Two-Stage CMOS Op-Amp | Miller-compensated 1.2 V op-amp with a 1 kOhm nulling resistor; 51.279 dB gain, 41.244 MHz UGB, approximately 73 degrees phase margin, and approximately 142 uW | Completed schematic-level baseline |
| Photodiode Sensor Analog Front End | LTspice signal-chain study using an AD8629 TIA and second-order Sallen-Key filtering; 1.07 MHz reported TIA bandwidth with a 1.023 kHz filter design | Completed analog simulation study; source-file reproducibility update pending |
- CMOS differential pairs, active loads, current mirrors, biasing, gain stages, positive feedback, and regenerative comparators
- Transimpedance amplifiers, photodiode interfaces, active filters, signal conditioning, and mixed-signal modeling
- Frequency compensation, loop stability, gain/UGB/phase-margin extraction, CMRR, PSRR, slew rate, settling, and output swing
- Comparator delay/reset timing, kickback, mismatch offset, transient noise, output loading, energy, and PVT analysis
- Cadence Virtuoso, Spectre, ADE, LTspice, Verilog-A exposure, Python-based result processing, Git, and technical reporting
Every public project separates:
- simulated results from targets and estimates;
- nominal schematic verification from PVT/statistical verification;
- completed work from ongoing integration;
- recomputed checks from source-reported values;
- portable reference files from proprietary models and design databases.
That distinction matters to me: a clean schematic is only the start of an engineering story; the assumptions, measurement definitions, failure limits, and unresolved verification work must also be visible.
- B.Tech, Electronics and Communication Engineering — Amrita Vishwa Vidyapeetham, expected 2027
- NPTEL Analog IC Design — 71%
- Based in Coimbatore, Tamil Nadu, India