Issues

• PerformanceCounterPlugin: unimplemented ("dummy") HPM CSRs are allowed without the counteren permission checks

  SpinalHDL/VexiiRiscv#196 · Filter by author qinkejiu opened on Oct 11, 2026

• h: SCOUNTEREN is not banked for VS/VU — guest counter access is governed by the host s.counteren bit

  SpinalHDL/VexiiRiscv#195 · Filter by author qinkejiu opened on Oct 11, 2026

• About CFU Request/Reorder

  SpinalHDL/VexiiRiscv#155 · Filter by author Jzjerry opened on Aug 1, 2026
  15

• [DISCUSSION] Unified configuartion database for VexiiRiscv

  SpinalHDL/VexiiRiscv#152 · Filter by author inochisa opened on Jul 21, 2026

• MMU memory access in cacheless LSU is bypassed without PMP check.

  SpinalHDL/VexiiRiscv#145 · Filter by author inochisa opened on Jul 9, 2026
  2

• Are bitmanip extensions (Zba, Zbb, Zbc, Zbs) still experimental, can we add them to the README and the RTD ?

  SpinalHDL/VexiiRiscv#140 · Filter by author mrcmry opened on Jun 7, 2026
  2

• Is software prefetch (Zicbop from CMO) fully or partially implemented ?

  SpinalHDL/VexiiRiscv#139 · Filter by author mrcmry opened on Jun 7, 2026

• Issue with embedding VexiiRiscv into larger design

  SpinalHDL/VexiiRiscv#134 · Filter by author jdavidberger opened on May 28, 2026
  1

• Request for Zacas extension support

  SpinalHDL/VexiiRiscv#125 · Filter by author inochisa opened on Apr 14, 2026
  5

• Separate instruction and data memories

  SpinalHDL/VexiiRiscv#124 · Filter by author Rishu31 opened on Apr 2, 2026
  3

• Adding SDRAM to MicroSoC

  SpinalHDL/VexiiRiscv#122 · Filter by author RossComputerGuy opened on Mar 15, 2026
  3

• MRET causes illegal instruction trap after ECALL in/from M-Mode

  SpinalHDL/VexiiRiscv#117 · Filter by author Matze584 opened on Feb 12, 2026
  3

• Strange CPU Behavior attempting to port from VexRiscv to VexiiRiscv

  SpinalHDL/VexiiRiscv#114 · Filter by author polymerizedsage opened on Feb 6, 2026
  7

• Redundant tracer initialization for harts

  SpinalHDL/VexiiRiscv#111 · Filter by author ISHKAFEL09 opened on Jan 30, 2026
  1

• How to use external JTAG (CMSIS-DAP) with Vexii MicroSoc? (Beginner)

  SpinalHDL/VexiiRiscv#105 · Filter by author princesuman2004 opened on Jan 9, 2026
  3

• Examples for simulate SoC with spi flash?

  SpinalHDL/VexiiRiscv#102 · Filter by author Jzjerry opened on Dec 22, 2025
  6

• There is an inconsistency in mie.LCOFIE

  SpinalHDL/VexiiRiscv#96 · Filter by author fly-1011 opened on Nov 16, 2025
  2

• Trying to connect a LsuL1Cmd port from external units (like CFU) to CPU

  SpinalHDL/VexiiRiscv#80 · Filter by author Jzjerry opened on Sep 3, 2025
  6

• [Feature request] Zmmul extension, no division

  SpinalHDL/VexiiRiscv#73 · Filter by author jrmoserbaltimore opened on Aug 22, 2025
  3

• Disable LSU Cache on LiteX SoC

  SpinalHDL/VexiiRiscv#68 · Filter by author mkuhn99 opened on Aug 1, 2025
  1

• How to tunnel VexiiRiscv Debug port using BSCANE2?

  SpinalHDL/VexiiRiscv#58 · Filter by author Matze584 opened on May 27, 2025
  7

• [Feature Request] Vector extensions

  SpinalHDL/VexiiRiscv#57 · Filter by author jrmoserbaltimore opened on May 24, 2025
  5

• "Hello world" tutorial fails to compile

  SpinalHDL/VexiiRiscv#56 · Filter by author NikkiOfTheValley opened on May 23, 2025

• Support for vectored interrupt mode?

  SpinalHDL/VexiiRiscv#53 · Filter by author Matze584 opened on Apr 20, 2025
  3

• How to extract RS1/RS2 value for debugging?

  SpinalHDL/VexiiRiscv#46 · Filter by author esyvjlomh opened on Mar 19, 2025