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native-int: TPIDR_EL0/TPIDRRO_EL0 reads stay inside regions - #60

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dylanneve1 merged 1 commit into
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perf/native-int-sysreg
Oct 22, 2026
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System-register reads that are plain 64-bit CPU-state fields (no access check, read function, constant or I/O flag) become a native-int load from the CPU state instead of ending the region. At EL0 that means TPIDR_EL0 and TPIDRRO_EL0, which iOS reads on every TLS access. The SIT op is used only if the instruction has emitted no TCG op before that point; writes are unchanged.

Testing: native_int_check.S test 7 reads both registers in the middle of ALU code, after an EL0 MSR TPIDR_EL0 and with TPIDRRO_EL0 set at EL1. run-a13-tests.py passes 41/41 on an M1 macOS build.

🤖 Generated with Claude Code

…er fields (TPIDR_EL0, TPIDRRO_EL0)

A system-register read with no access check, read function, constant or
I/O flag (at EL0: TPIDR_EL0 and TPIDRRO_EL0, iOS's thread pointers) is a
64-bit load from the CPU state. It becomes a SIT_LDENV op instead of
ending the native-int region, provided the instruction has emitted no TCG
op before reaching that point. native_int_check.S test 7 reads both in the
middle of ALU code.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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dylanneve1 merged commit 2e1c79f into master Oct 22, 2026
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dylanneve1 deleted the perf/native-int-sysreg branch November 2, 2026 01:56
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