I'm a Computer Engineering student pursuing a dual degree at Purdue University and Egypt University of Informatics, with a passion for hardware design, computer architecture.

My work spans from low-level RTL design and ASIC implementation to high-level data engineering pipelines. I'm love by building systems that are both elegant and performant.

Key Focus Areas:

• 🔧 Digital hardware design (FPGA, ASIC, RTL verification)
• 🏗️ Computer architecture and systems optimization
• 📊 Data engineering and real-time anomaly detection
• 🤖 ML-systems integration

Aug 2025 – Jan 2026 | Miami, FL

• Engineered preprocessing pipelines for real-time anomaly detection dashboard monitoring ship engine telemetry across 3 vessels
• Parsed, cleaned, and aligned 10M+ time-series sensor readings, resolving timestamp inconsistencies and missing-value gaps
• Built robust data infrastructure for continuous fleet monitoring

Aug 2025 – May 2026 | West Lafayette, IN

• TA for Discrete Mathematics (Fall 2025) and ASIC Design Lab (Spring 2026), supporting ~150 students/semester
• Led weekly office hours, recitations, and provided detailed feedback on assignments, labs, and exams

SystemVerilog · QuestaSim · Vivado · FPGA

Architected a dual-core RISC-V processor featuring:

• 5-stage pipeline with data/instruction caches
• Shared bus controller with full hazard detection and forwarding logic
• Verified via QuestaSim testbenches and custom RISC-V assembly
• Synthesized in Vivado, achieved timing closure at 60 MHz on FPGA

SystemVerilog · Design Compiler · ASIC Design Flow

Designed an N×N systolic array accelerator for deep learning matrix multiplication:

• Achieved O(N) throughput vs. O(N³) serial baseline through spatial data reuse
• Complete ASIC design flow with synthesis and place-and-route
• Optimized for area, power, and timing

Python · ROS 2 · Gazebo

Developed A*-based path planning module for autonomous drones in dynamic environments:

• Real-time obstacle avoidance and dynamic map updates
• Comprehensive unit test suite with ~80% code coverage
• 4-person senior design team collaboration

Hardware & Design:

• HDL: SystemVerilog, Verilog, VHDL, RISC-V ISA
• Specialties: RTL design, pipelining, cache architecture, ASIC flow
• EDA Tools: QuestaSim, Quartus Prime, Vivado, Design Compiler

Software & Platforms:

• Languages: C, C++, Python
• ML/Data: TensorFlow, Keras
• Tools & Platforms: Git, Linux, ROS 2