All pull requests

Pull requests

• [Loom] Author finite pipelines and owned channels in C++

  #2487·benvanik opened Oct 30, 2026Collaborator·

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• [Loom] Select sparse mixed vector construction

  #2485·benvanik opened Oct 30, 2026Collaborator·

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• [Loom] Preserve large streamed tool-call responses

  #2484·benvanik opened Oct 30, 2026Collaborator·

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• [Loom] Preserve signed coordinates in SPIR-V index scaling

  #2483·benvanik opened Oct 30, 2026Collaborator·

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• [Loom] Consolidate AMD GPU execution on the native HAL

  #2482·benvanik opened Oct 30, 2026Collaborator·

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• [libamdf] Expose caller-scheduled native device telemetry

  #2378·benvanik opened Oct 27, 2026Collaborator·

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• [Loom] Stream continuing text into independently batched speech

  #2132·benvanik opened Oct 20, 2026Collaborator·

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• [Loom] Multi-target composable FFT research prototype

  #1954·benvanik opened Oct 17, 2026Collaborator·

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• [Loom] Validate native cooperative matrix types against target properties

  #1918·benvanik opened Oct 16, 2026Collaborator·

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• [Loom] Share the configured compiler through libloomc

  #1682·stellaraccident opened Oct 14, 2026Collaborator·

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• [HAL/AMDGPU] Provision two queues for multi-queue tests

  #1134·Groverkss opened Sep 29, 2026·

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• [HAL/AMDGPU] Map gfx1250 queue resources across XCDs

  #1133·Groverkss opened Sep 29, 2026·

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• [AMDGPU] Support gfx1250-strict ISA across targets

  #1132·Groverkss opened Sep 29, 2026·

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• [HIP] Fall back uncached virtual memory placement

  #1084·AWoloszyn opened Sep 28, 2026Collaborator·

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• [HIP] Classify array storage overflow as exhaustion

  #1083·AWoloszyn opened Sep 28, 2026Collaborator·

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• chore: add security scanning workflows

  #1081·haribabug opened Sep 28, 2026·

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• [HIP] Expand graph construction, execution, and stream capture

  #914·AWoloszyn opened Sep 23, 2026Collaborator·

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• [Experiment] AMDGPU SDMA transfer/compute overlap

  #625·Groverkss opened Sep 17, 2026·

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• [HIP] Implement IPC memory and event handles

  #624·zjgarvey opened Sep 17, 2026Collaborator·3/3·

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• [HRX] Align graph executable block storage

  #623·zjgarvey opened Sep 17, 2026Collaborator·2/3·

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• [HAL/AMDGPU] Support both ROCr queue creation interfaces

  #617·zjgarvey opened Sep 17, 2026Collaborator·1/3·

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• [HAL/AMDGPU] Add fixed masked execution queues

  #444·zjgarvey opened Aug 27, 2026Collaborator·

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• [HRX/CUDA] Fix inverted query results and build the binding under Bazel

  #383·zjgarvey opened Aug 17, 2026Collaborator·

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• [HAL/AMDGPU] Snapshot static indirect dispatch tables at queue issue

  #376·benvanik opened Aug 17, 2026Collaborator·

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• [AMDGPU] Emplace implicit kernargs per field to support unaligned/partial hidden blocks

  #201·zjgarvey opened Jul 20, 2026Collaborator·

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