cpu/nrf5x_common: implement periph/gpio_ll{,_irq}

[maribu]

Contribution description

Implements gpio_ll and gpio_ll_irq for NRF5x.

Testing procedure

make BOARD=nrf52840dk -C tests/periph_gpio_ll
make BOARD=nrf51dk -C tests/periph_gpio_ll

Both are passing locally for me

Issues/PRs references

Depends on and includes: #16787

[maribu]

Output of the benchmark on the nRF52840-DK:

Help: Press s to start test, r to print it is ready
START
main(): This is RIOT! (Version: 2022.07-devel-163-gea5f8-gpio_ll/nrf5x)

Benchmarking GPIO APIs
======================

estimating loop overhead for compensation
-----------------------------------------
2345 us for 50000 iterations

periph/gpio: Using 2x gpio_set() and 2x gpio_clear()
---------------------------------------------------
50000 iterations took 51563 us (53908 us uncompensated)
Two square waves pins at       969687 Hz (      927506 Hz uncompensated)
~66 CPU cycles per square wave period (~69 cycles uncompensated)
:'-(

periph/gpio_ll: Using gpio_ll_set() and gpio_ll_clear()
-------------------------------------------------------
50000 iterations took 1562 us (3907 us uncompensated)
Two square waves pins at     32010243 Hz (    12797542 Hz uncompensated)
~2 CPU cycles per square wave period (~5 cycles uncompensated)
:-D

periph/gpio: Using 4x gpio_toggle()
-----------------------------------
50000 iterations took 56250 us (58595 us uncompensated)
Two square waves pins at       888888 Hz (      853315 Hz uncompensated)
~72 CPU cycles per square wave period (~75 cycles uncompensated)
:'-(

periph/gpio_ll: Using 2x gpio_ll_toggle()
-----------------------------------------
50000 iterations took 14063 us (16408 us uncompensated)
Two square waves pins at      3555429 Hz (     3047294 Hz uncompensated)
~18 CPU cycles per square wave period (~21 cycles uncompensated)
:'-(

periph/gpio: Using 4x gpio_write()
----------------------------------
50000 iterations took 56250 us (58595 us uncompensated)
Two square waves pins at       888888 Hz (      853315 Hz uncompensated)
~72 CPU cycles per square wave period (~75 cycles uncompensated)
:'-(

periph/gpio_ll: Using 2x gpio_ll_write()
----------------------------------------
50000 iterations took 1562 us (3907 us uncompensated)
Two square waves pins at     32010243 Hz (    12797542 Hz uncompensated)
~2 CPU cycles per square wave period (~5 cycles uncompensated)
:-D


TEST SUCCEEDED
{ "threads": [{ "name": "main", "stack_size": 1536, "stack_used": 440 }]}

So gpio_ll_set(), gpio_ll_clear(), and gpio_ll_write() perform optimal (one CPU cycle per call). gpio_ll_toggle() is suboptimal, as there is no hardware acceleration for it (or I couldn't find it in the datasheet). 9 CPU cycles per access is a bit unpleasant, but a read-modify-write sequence by hand with IRQ disabling is expected to be non-optimal.

[benpicco]

Please squash

[maribu]

The nRF9x has a different layout of the memory mapped I/O area, but the start address remaimed the same. There is value in using the start adress of the are father than e.g. the lowest GPIO register, as the least significant bytes are all zeros, allowing to construct the adress via a load immediate instruction (or st least I believe so). I opted for just creating a define for that by hand.

With that, now all is green.

[maribu]

@benpicco are you fine with this? (Note that NRF5X_IO_AREA_START is defined in this header, so it will be needed to be maintained by us. But I don't expect the I/O memory area to be mapped differently for future nRF MCUs that can share the same GPIO driver.)

[benpicco]

Sure, that will work