A RISC-V simulator for computer architecture education, based on the RV64-IM ISA. Supports multiple execution modes, pipeline simulation, out-of-order execution, branch prediction, and multi-core cache coherence — suitable for architecture lab experiments and performance analysis.
- RV64-IM: Base integer ISA + multiply/divide extension
- Zicsr: CSR instructions (
mhartid,mcycle, etc.), supportsrdcyclefor benchmarking - System instructions: FENCE, FENCE.I, ECALL, MRET, EBREAK
| Mode | Description | Flag |
|---|---|---|
| Functional (default) | Interpreted execution; correctness baseline | (default) |
| In-order pipeline | 5-stage IF/ID/EX/MEM/WB with hazard handling | --inorder |
| Out-of-order (Tomasulo) | ROB + reservation stations + physical register file + RAT/RRAT | --ooo |
- Branch Target Buffer (BTB)
- Tournament predictor: local history (LHT/LPHT) + global history (GHR/GPHT) + meta selector
- Two-level cache: private L1I/L1D per core + shared L2
- Configurable sets (
sbits) and ways (w); fixed 64-byte cache lines - LRU replacement, write-back + write-allocate
- Dual-hart simulation with independent L1I/L1D, pipeline/OOO state, and branch predictor per core
- Write-invalidate cache coherence protocol
- FENCE instruction enforces memory ordering across OOO cores
- Serial (UART output for bare-metal programs)
- Flash, RTC, VGA, Keyboard
gcc / g++ llvm-11 (for disassembly) make
makemake test # runs test/kernel.bin; exit code 0 = pass./build/sustemu <image.bin> # functional mode
./build/sustemu --inorder <image.bin> # in-order pipeline
./build/sustemu --ooo <image.bin> # out-of-order execution
./build/sustemu --ooo --dual <image.bin> # dual-core OOOcd test/dual && make
./build/sustemu --ooo --dual test/dual/dual.binInspired by NEMU (Nanjing University emulator). Extended for architecture education with pipeline, OOO, branch prediction, and multi-core modules.