Kristina prevent code overwrite

src/Instruction.hs

@@ -20,8 +20,9 @@ module Instruction
     getRs2,
     isBreak,
     isCall,
-    isNopBranchFirstCycle,
+    isNopJumpFirstCycle,
     isNopLoadHazardFirstCycle,
+    isNopStoreHazardFirstCycle,
     isNopHalted,
     break,
     loadHazard,
@@ -106,21 +107,25 @@ data IOperation
 
 -- | Reason for replacing an instruction with a nop. Some of these can be collapsed if we want to optimize later.
 data Reason4Stall
-  = -- | We took a branch 1 cycle ago.
-    BranchFirstCycle
-  | -- | We took a branch 2 cycles ago.
-    BranchSecondCycle
-  | -- | A load hazard occurred 1 cycle ago.
+  = -- | First instruction discarded because of a jump.
+    JumpFirstCycle
+  | -- | Second instruction discarded because of a jump.
+    JumpSecondCycle
+  | -- | First instruction discarded because of a load hazard.
     LoadHazardFirstCycle
-  | -- | A load hazard occurred 2 cycles ago.
+  | -- | Second instruction discarded because of a load hazard.
     LoadHazardSecondCycle
+  | -- | First instruction discarded because of a store hazard.
+    StoreHazardFirstCycle
+  | -- | Second instruction discarded because of a store hazard.
+    StoreHazardSecondCycle
   | -- | No instruction read because of memory bus overload.
     MemoryBusBusy
-  | -- | First cycle.
-    FirstCycle
   | -- | Failed to decode an instruction.
     DecodeFail
-  | -- | PC has halted.
+  | -- | First cycle.
+    FirstCycle
+  | -- | The core has halted.
     Halted
   deriving (Eq, Show, Generic, NFDataX, Binary)
 
@@ -443,14 +448,18 @@ isStore :: Instruction -> Bool
 isStore (SType {}) = True
 isStore _ = False
 
-isNopBranchFirstCycle :: Instruction -> Bool
-isNopBranchFirstCycle (Nop BranchFirstCycle) = True
-isNopBranchFirstCycle _ = False
+isNopJumpFirstCycle :: Instruction -> Bool
+isNopJumpFirstCycle (Nop JumpFirstCycle) = True
+isNopJumpFirstCycle _ = False
 
 isNopLoadHazardFirstCycle :: Instruction -> Bool
 isNopLoadHazardFirstCycle (Nop LoadHazardFirstCycle) = True
 isNopLoadHazardFirstCycle _ = False
 
+isNopStoreHazardFirstCycle :: Instruction -> Bool
+isNopStoreHazardFirstCycle (Nop StoreHazardFirstCycle) = True
+isNopStoreHazardFirstCycle _ = False
+
 isNopHalted :: Instruction -> Bool
 isNopHalted (Nop Halted) = True
 isNopHalted _ = False

src/Leak/MonitorPC/MonitorLeak.hs

@@ -83,4 +83,4 @@ monitorJumpAddress :: LeakMonitor (Core.State Identity) (Core.Input Identity) (C
 monitorJumpAddress = LeakMonitor leak id
  where
   leak :: Core.State Identity -> Core.Input Identity -> (Core.State Identity, Maybe Address)
-  leak s i = let (s', _) = Core.circuit s i in (s', Core.ctrlExAddress $ Core.stateCtrl s')
+  leak s i = let (s', _) = Core.circuit s i in (s', Core.ctrlExJumpAddr $ Core.stateCtrl s')

src/Leak/MonitorPC/PC.hs

@@ -51,13 +51,13 @@ proj s = (ts, ss)
           Sim.stateExPc = if halted then 0 else Core.stateExPc s,
           Sim.stateExInstr = if halted then Leak.nop' else Leak.toLeakInstr $ Core.stateExInstr s,
           Sim.stateMemInstr = if halted then Leak.nop' else killJump $ Leak.toLeakInstr $ Core.stateMeInstr s,
-          Sim.stateMemRes = if halted then 0 else unAccess $ Core.stateMeAluRes s,
+          Sim.stateMemRes = if halted then 0 else unAccess $ Core.stateMeRes s,
           Sim.stateWbInstr = if halted then Leak.nop' else killJump $ Leak.toLeakInstr $ Core.stateWbInstr s,
-          Sim.stateWbRes = if halted then 0 else unAccess $ Core.stateWbAluRes s,
+          Sim.stateWbRes = if halted then 0 else unAccess $ Core.stateWbRes s,
           Sim.stateHalt = halted,
           Sim.stateStallFetch = not halted && toStallFetch (Core.stateCtrl s),
           Sim.stateStallDecode = not halted && toStallDecode (Core.stateCtrl s),
-          Sim.stateJumpAddr = if halted then Nothing else Core.ctrlExAddress $ Core.stateCtrl s,
+          Sim.stateJumpAddr = if halted then Nothing else Core.ctrlExJumpAddr $ Core.stateCtrl s,
           Sim.stateFirstCycle = not halted && isNothing (Core.stateHalt s)
         }
 
@@ -68,9 +68,9 @@ proj s = (ts, ss)
     toStallFetch :: Core.Control Identity -> Bool
     toStallFetch ctrl =
       Core.ctrlMeMemInstr ctrl
-        || isJust (Core.ctrlExAddress ctrl)
+        || isJust (Core.ctrlExJumpAddr ctrl)
 
     toStallDecode :: Core.Control Identity -> Bool
     toStallDecode ctrl =
       isJust (Core.ctrlDeLoadHazard ctrl)
-        || isJust (Core.ctrlExAddress ctrl)
+        || isJust (Core.ctrlExJumpAddr ctrl)

src/Leak/PC/Leak.hs

@@ -175,7 +175,7 @@ decode = do
   mJumpAddr <- gets stateJumpAddr
   firstCycle <- gets stateFirstCycle
 
-  let branch_first_cycle = Instr.isNopBranchFirstCycle exInstr
+  let branch_first_cycle = Instr.isNopJumpFirstCycle exInstr
   let load_hazard_current_cycle = Instr.loadHazard instr exInstr
   let load_hazard_first_cycle = Instr.isNopLoadHazardFirstCycle exInstr
   let call_current_cycle = Instr.isCall exInstr
@@ -184,9 +184,9 @@ decode = do
 
   let ir' =
         -- If a branch was taken in this cycle, we stall.
-        if isJust mJumpAddr then Instr.Nop Instr.BranchFirstCycle
+        if isJust mJumpAddr then Instr.Nop Instr.JumpFirstCycle
         -- If a branch was taken in the previous cycle, we stall.
-        else if branch_first_cycle then Instr.Nop Instr.BranchSecondCycle
+        else if branch_first_cycle then Instr.Nop Instr.JumpSecondCycle
         -- If there is a load hazard with the instruction executed in this cycle, we stall.
         else if load_hazard_current_cycle then Instr.Nop Instr.LoadHazardFirstCycle
         -- If there was a load hazard in the previous cycle, we stall.

src/Leak/PC/PC.hs

@@ -82,16 +82,16 @@ proj s = (ts, ss)
           Leak.stateExPc = Core.stateExPc s,
           Leak.stateExInstr = Core.stateExInstr s,
           Leak.stateMemInstr = Core.stateMeInstr s,
-          Leak.stateMemRes = unAccess $ Core.stateMeAluRes s,
-          Leak.stateMemVal = unAccess $ Core.stateMeStoreRes s,
+          Leak.stateMemRes = unAccess $ Core.stateMeRes s,
+          Leak.stateMemVal = pack $ Core.stateMeAddr s, -- this is wrong, I am just making it compile
           Leak.stateWbInstr = Core.stateWbInstr s,
-          Leak.stateWbRes = unAccess $ Core.stateWbAluRes s,
+          Leak.stateWbRes = unAccess $ Core.stateWbRes s,
           Leak.stateRegFile = Core.stateRegFile s,
           Leak.stateMeMemInstr = Core.ctrlMeMemInstr $ Core.stateCtrl s,
           Leak.stateHalt = Core.stateHalt s,
           Leak.stateMeRegFwd = fmap (second unAccess) $ Core.ctrlMeRegFwd $ Core.stateCtrl s,
           Leak.stateWbRegFwd = fmap (second unAccess) $ Core.ctrlWbRegFwd $ Core.stateCtrl s,
-          Leak.stateJumpAddr = Core.ctrlExAddress $ Core.stateCtrl s,
+          Leak.stateJumpAddr = Core.ctrlExJumpAddr $ Core.stateCtrl s,
           Leak.stateDeLoadHazard = Core.ctrlDeLoadHazard $ Core.stateCtrl s,
           Leak.stateDeCall = False,
           Leak.stateFirstCycle = False
@@ -107,7 +107,7 @@ proj s = (ts, ss)
           Sim.stateHalt = Core.stateHalt s,
           Sim.stateHaltPending = Core.stateHaltPending s,
           Sim.stateMeMemInstr = Core.ctrlMeMemInstr $ Core.stateCtrl s,
-          Sim.stateJumpAddr = Core.ctrlExAddress $ Core.stateCtrl s,
+          Sim.stateJumpAddr = Core.ctrlExJumpAddr $ Core.stateCtrl s,
           Sim.stateDeLoadHazard = Core.ctrlDeLoadHazard $ Core.stateCtrl s,
           Sim.stateDeCall = False,
           Sim.stateFirstCycle = False

src/Leak/PC/Sim.hs

@@ -114,9 +114,9 @@ decode = do
 
   let ir' =
         -- If a branch was taken in this cycle, we stall.
-        if isJust mJumpAddr then Leak.Instr (Leak.Nop Instr.BranchFirstCycle) (Nothing, Nothing)
+        if isJust mJumpAddr then Leak.Instr (Leak.Nop Instr.JumpFirstCycle) (Nothing, Nothing)
         -- If a branch was taken in the previous cycle, we stall.
-        else if branch_first_cycle then Leak.Instr (Leak.Nop Instr.BranchSecondCycle) (Nothing, Nothing)
+        else if branch_first_cycle then Leak.Instr (Leak.Nop Instr.JumpSecondCycle) (Nothing, Nothing)
         -- If there is a load hazard with the instruction executed in this cycle, we stall.
         else if load_hazard_current_cycle then Leak.Instr (Leak.Nop Instr.LoadHazardFirstCycle) (Nothing, Nothing)
         -- If there was a load hazard in the previous cycle, we stall.
@@ -147,7 +147,7 @@ decode = do
       }
   where
     instrBase (Leak.Instr b _) = b
-    isNopBranchFirstCycle (Leak.Instr (Leak.Nop Instr.BranchFirstCycle) _) = True
+    isNopBranchFirstCycle (Leak.Instr (Leak.Nop Instr.JumpFirstCycle) _) = True
     isNopBranchFirstCycle _ = False
     isNopLoadHazardFirstCycle (Leak.Instr (Leak.Nop Instr.LoadHazardFirstCycle) _) = True
     isNopLoadHazardFirstCycle _ = False

src/Leak/SecretPC/PC.hs

@@ -80,9 +80,8 @@ circuit (ts, ss) input = ((ts', ss'), addr)
 proj' :: Core.State PubSec -> SimState
 proj' s =
   s
-    { Core.stateMeAluRes = censor (Core.stateMeAluRes s),
-      Core.stateMeStoreRes = censor (Core.stateMeStoreRes s),
-      Core.stateWbAluRes = censor (Core.stateWbAluRes s),
+    { Core.stateMeRes = censor (Core.stateMeRes s),
+      Core.stateWbRes = censor (Core.stateWbRes s),
       Core.stateRegFile = let RegFile rf = Core.stateRegFile s in RegFile (Clash.Prelude.map censor rf),
       Core.stateCtrl =
         let c = Core.stateCtrl s

test/Spec.hs

@@ -289,6 +289,9 @@ instance {-# OVERLAPPING #-} (Access f) => Arbitrary (Control f) where
       <*> arbitrary
       <*> arbitrary
       <*> arbitrary
+      <*> arbitrary
+      <*> arbitrary
+      <*> arbitrary
       <*> genMaybeRegFwd
       <*> genMaybeRegFwd
     where