Describe the bug
When MRET with mstatus MPP<M and MPRV=1, in this case, MPP=U: "An MRET or SRET instruction that changes the privilege mode to a mode less privileged than M also sets MPRV=0."- 3.1. Machine-Level CSRs | Page 35 The RISC-V Instruction Set Manual, Volume II

Therefore, in gem5 bit 17(MPRV) of mstatus should be 0 instead of 1.
To Reproduce
Try bin file /nfs/home/liuhaoyuan/GEM5/img_file/seeds_998_.img
Expected behavior
Difftest fail
Necessary information on versions
- XS-GEM5 version: [fix-mstatus]
- NEMU version used as reference design: [newest ]
Describe the bug
When MRET with mstatus MPP<M and MPRV=1, in this case, MPP=U: "An MRET or SRET instruction that changes the privilege mode to a mode less privileged than M also sets MPRV=0."- 3.1. Machine-Level CSRs | Page 35 The RISC-V Instruction Set Manual, Volume II
To Reproduce
Try bin file /nfs/home/liuhaoyuan/GEM5/img_file/seeds_998_.img
Expected behavior
Difftest fail
Necessary information on versions