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perf(v5e): SX1262 SPI 125 kHz -> 4 MHz + TCXO wakeup 10 -> 5 ms (1.72x downlink) - #476

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perf(v5e): SX1262 SPI 125 kHz -> 4 MHz + TCXO wakeup 10 -> 5 ms (1.72x downlink)#476
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feat/usp-radiofrom
perf/v5e-sx1262-spi-tcxo-timing

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Summary

USP LoRa downlink at P4_GFSK_75K was software-limited to ~2.5 kB/s (~27% of PHY). Per-frame RAM-trace instrumentation on the HIL bench (probes at ComQueue hand-off, UspRadio deferred TX, RAC submit, onPreTx, set_tx, TX_DONE, comStatus) produced this breakdown of the ~97 ms/frame cadence:

stage 125 kHz baseline 4 MHz 4 MHz + TCXO 5 ms
comStatus -> next frame at radio ~8.6 ms 2.4 ms 2.3 ms
dataIn -> deferred handler 0.7 ms 6.2 ms* 6.1 ms*
stop/submit/RAC/planner ~0.2 ms ~0.3 ms ~0.3 ms
onPreTx (SPI config + 249 B FIFO + set_tx) 30.7 ms 12.2 ms 7.2 ms
airtime (set_tx -> TX_DONE) 27.8 ms 27.8 ms 27.8 ms
TX_DONE -> comStatus 3.7 ms 2.7 ms 2.8 ms

* includes the deliberate bounded re-arm-skip wait; overlaps the pipeline hop.

Two board-DTS costs dominate the overhead:

  1. spi-max-frequency = 125000 (bring-up value) — ~18 ms/frame of pure SPI time.
  2. tcxo-wakeup-time = 10 — the radio planner sleeps the radio after every task, so the TCXO restart is paid per frame.

Measurements (178,704 B //dl200k.bin SD-file downlink over RF, 248 B frames)

  • baseline: 69.8-71.5 s (2500-2562 B/s), 181-214 RateGroupCycleSlip/run
  • SPI 4 MHz: 45.79 s (3903 B/s), 1 cycle slip
  • SPI 4 MHz + TCXO 5 ms: 41.44 s (4312 B/s, 1.72x), 5 cycle slips
  • All downlinked files byte-identical (md5 911c2ce7...) to baseline copies
  • Bidirectional link, authenticated RF commanding, and P0<->P4 profile switching re-verified after each change

Caveats / follow-ups

  • TCXO 5 ms is HWIL-validated but should be confirmed against the E22-400M30S TCXO startup spec before flight; keep 10 ms if the spec disagrees (SPI-only change alone is 1.53x).
  • The structural fix — lazy radio sleep between back-to-back TX tasks in the radio planner (saves the remaining ~5-7 ms wake cost) — is a usp fork change, tracked separately.
  • Remaining software floor after this PR is ~15 ms/frame (bounded re-arm window + residual SPI/handshake); airtime is now >60% of the frame period.

🤖 Generated with Claude Code

The USP LoRa downlink at P4_GFSK_75K was software-limited to ~2.5 kB/s
(~27% of PHY): per-frame RAM-trace instrumentation on the HIL bench showed
~31 ms of the ~50 ms non-airtime overhead was onPreTx SPI work (pkt params
+ 249 B FIFO upload + set_tx) at the 125 kHz bring-up SPI clock, and the
radio planner's sleep-after-every-task re-pays the DTS TCXO wakeup delay
on every frame.

HWIL 2026-07-24 (v5e <-> GRC-USP, 178,704 B //dl200k.bin SD file downlink,
248 B frames, radio-only path):
- baseline:               69.8-71.5 s (2500-2562 B/s), 181-214 cycle slips
- SPI 4 MHz:              45.79 s (3903 B/s), 1 cycle slip
- SPI 4 MHz + TCXO 5 ms:  41.44 s (4312 B/s, 1.72x), 5 cycle slips
All downlinked files byte-identical to baseline; bidirectional link,
authenticated RF commanding, and profile switching verified at each step.

TCXO note: confirm 5 ms against the E22-400M30S TCXO startup spec before
flight; the structural fix (lazy radio sleep between back-to-back TX
tasks) belongs in the usp radio planner and is tracked separately.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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