 "There's no such thing as psychics— just paying attention to details." |
Bridging digital microarchitecture and physical silicon from writing cycle-accurate RTL and constrained-random testbenches to closing timing at the gate level.
Deep Diving Into: UVM Methodologies, Functional Coverage, and AMBA AXI4 Protocols.
nikunjbhatt244@gmail.com
| Project | Stack & Flow | Highlights & Engineering Impact |
|---|---|---|
| INT8 Systolic Array AI Accelerator | SystemVerilog Verilator Yosys OpenLane (Sky130) |
Architected a 4×4 weight-stationary systolic array with skew buffers and a 16-channel requantization pipeline. Achieved 100 MHz timing closure on SkyWater 130nm (~17.9k standard cells). |
| Sentry-AI Edge Accelerator | Verilog Caravel / chipIgnite |
Designed an ultra-low-power digital edge inference pipeline targeting open-source silicon integration. |
| 4-Stage Pipelined RISC Processor | Verilog Synopsys DC |
Built a custom IF/ID/EX/WB core featuring hardware hazard detection and data-forwarding paths to eliminate pipeline stalls. |
| 32-Bit ALU & CRV Testbench | SystemVerilog ModelSim |
Implemented arithmetic/logical datapaths with zero-flag logic, verified via self-checking constrained-random testbenches. |
HDL & Verification
ASIC Flow, Simulation & FPGA
Golden Reference Modeling & Systems
