Skip to content
View Najid-Villana's full-sized avatar

Highlights

  • Pro

Block or report Najid-Villana

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Najid-Villana/README.md

👋 Hi, I'm Muhammad Najid

🎓 Electrical Engineer (Computer Systems Engineering) passionate about Digital IC Design, RTL Development, FPGA Design, and Embedded Systems.

🚀 About Me

  • 🔭 Currently working on Digital IC Design & Verification
  • 🌱 Learning SystemVerilog, UVM, ASIC Design Flow, and Advanced FPGA Development
  • 💻 Experienced with Verilog/SystemVerilog, Xilinx Vivado, STM32, FreeRTOS, C/C++, Python, and Git
  • 🤖 Interested in combining AI with Embedded and Hardware Systems
  • 🎯 Goal: Become an RTL Design / FPGA / ASIC Design Engineer

🛠️ Technical Skills

Languages

  • Verilog
  • System Verilog
  • C
  • C++
  • Python
  • Assembly

Digital Design

  • RTL Design
  • Digital Logic Design
  • FPGA Development
  • Finite State Machines (FSM)
  • Combinational & Sequential Logic
  • Computer Architecture

Tools

  • Xilinx Vivado
  • Cadence
  • MPLab
  • STM32 Cube IDE
  • Linux
  • VS Code

Embedded Systems

  • STM32
  • FreeRTOS
  • GPIO
  • UART
  • SPI
  • I²C
  • Timers
  • PWM
  • ADC
  • DAC

🤝 Looking to Collaborate

I'm interested in collaborating on:

  • RTL Design
  • FPGA Projects
  • Digital IC Design
  • Embedded Systems
  • Open Source Hardware
  • SystemVerilog/UVM Projects

📫 Connect With Me

⚡ Fun Fact

I enjoy turning digital logic into working hardware and continuously learning new technologies in FPGA, ASIC, and Embedded Systems.

⭐ Thanks for visiting my profile! Feel free to explore my repositories and connect with me.

Pinned Loading

  1. KNN-Classifier-in-Verilog KNN-Classifier-in-Verilog Public

    This project is build during The Digital IC Design and Verification Training sponsored by Government of Pakistan. This project shows a KNN algorithm applied using verilog and Vivado.

    C

  2. Control-LED-using-Switches-on-ARTY-A7-FPGA Control-LED-using-Switches-on-ARTY-A7-FPGA Public

    Learning project on the Digilent Arty A7-100T FPGA — SystemVerilog designs exploring switches, LEDs, PWM, and XADC, built from scratch in Vivado.

    HTML

  3. 8-bit-Multiplier-using-Vivado-IP-Integrator 8-bit-Multiplier-using-Vivado-IP-Integrator Public

    8-bit unsigned multiplier design using Xilinx Vivado IP Integrator with behavioral simulation, pipelined architecture, and comprehensive testbench.

    VHDL

  4. Traffic-Light-Controller Traffic-Light-Controller Public

    A priority-based traffic signal management system implemented in Verilog, combining vehicle and pedestrian traffic control with safety-critical guarantees.

    C

  5. 4-bit-ALU 4-bit-ALU Public

    A 4-bit Arithmetic Logic Unit (ALU) designed in Verilog HDL and simulated using Xilinx Vivado. The project implements fundamental arithmetic and logical operations including addition, subtraction, …

    C

  6. 7-Segment-Display-Decoder 7-Segment-Display-Decoder Public

    Verilog implementation of a 7-Segment Display Decoder with a comprehensive testbench for all hexadecimal inputs (0–F), simulated in Xilinx Vivado.

    C