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Add experimental SM100-optimized bulk causal conv1d forward - #798

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Add experimental SM100-optimized bulk causal conv1d forward#798
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@YangXu1990uiuc YangXu1990uiuc commented Aug 29, 2026

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Affected area

FE OSS kernels or CuTeDSL.

Summary

Downstream model impact (combined attribution)

On B200, BF16 batch-one fprop+bprop all-on proxies containing this causal-convolution forward feature measured, at 8K/16K/32K respectively: Qwen3.5-9B 32-layer decoder backbone 1.1530x / 1.1722x / 1.1931x; Qwen3.8-27B 64-layer decoder backbone 1.1354x / 1.1967x / 1.0898x; GLM-5.3-Flash 34-layer KDA substack 1.0732x / 1.0950x / 1.0966x; and the official-count Kimi-K3 feature substack 1.3567x / 1.3238x / 1.2189x. These are combined results: Qwen also changes GDN, SwiGLU, and SDPA; GLM also changes KDA; Kimi also changes KDA and SiTU. They are not marginal speedups attributable to #798 or assembled-model results. Qwen and GLM contain this exact current head; Kimi uses a patch-equivalent rebased implementation.

Add an experimental, independent, SM100-optimized bulk causal-conv1d forward API and CuTeDSL kernel for the BF16, width-4, fused-SiLU operation used by short-convolution model blocks.

The implementation supports:

  • dense [B, T, D] and packed [1, total_T, D] inputs;
  • packed boundaries supplied as device-resident int32 cumulative sequence lengths;
  • optional bias;
  • optional full-width [N, D, 4] initial and final states;
  • symbolic runtime T reuse for a compiled shape signature;
  • a 128-bit vec8 fast path on the explicitly admitted SM100-family and newer targets, plus a compile-time-selected scalar fallback for supported SM80-SM90 targets;
  • explicit/current PyTorch stream launch and allocator-lifetime recording;
  • device-side validation that traps invalid packed boundaries before the convolution launch.

No external causal-conv kernel implementation was copied. FLA is used only as an independently installed interoperability/performance comparison in the manual benchmark; permanent correctness tests use the in-tree PyTorch reference.

Why

The frontend has a decode-oriented causal-conv companion in #797, but no matching bulk/prefill primitive. This fills that forward feature gap with a standalone frontend implementation while keeping the contract narrow enough to validate and optimize independently.

Related issues

Related to #797.

API and compatibility impact

This adds the experimental CausalConv1dBulkFwdSm100 class and causal_conv1d_bulk_fwd_wrapper_sm100 convenience wrapper; the original suffix is retained while the API evolves. The exact functional targets are SM80/86/87/89/90/100/103/110/120/121. SM100/103/110/120/121 use the vec8 path when D is divisible by eight; SM80-SM90 use a compile-time scalar schedule. Unsupported architectures and inputs fail closed; there is no framework fallback, conversion, host synchronization, or backward implementation.

The API checks for nvidia-cutlass-dsl >= 4.7 before lazily importing the kernel. The repository-wide dependency floor is unchanged. The optional state layout is intended to be compatible with the pending decode companion in #797; cross-API state tests remain conditional on that PR landing.

Architecture policy and validation

Architecture admission and schedule selection are separate. The vec8 path contains mul.f32x2 / fma.rn.f32x2, whose PTX target floor is SM100. Pre-Blackwell targets therefore compile only the ordinary-FP32 scalar kernel, even when D % 8 == 0. The gate is an explicit target allowlist rather than an open-ended >= comparison because the current DSL does not accept every numerical capability between listed targets.

The benchmark harness itself runs on every functional target, requires neither ComputeLab nor Slurm, and records ordinary hardware/software metadata plus optional Slurm fields.

No performance numbers were collected outside B200. Functional validation:

  • ComputeLab A100 SM80, H200 SM90, and B200 SM100: complete GPU suite, 27 passed on each architecture.
  • ComputeLab GB110 bring-up board SM103 and RTX 5080 SM120: dense vec8 and scalar state/final-state smoke tests passed against the independent reference.
  • SM110 and SM121: API-equivalent CuTeDSL cross-compilation passed, including packed/state vec8; no runtime device was available, so these are compile-validated rather than runtime-validated.

ComputeLab B200 performance

Equal-layout cuDNN backend NWH baseline (current head)

The exact clean current head 678e3570272ced7009eadb9603b4eb911b76cb8a was rechecked on one NVIDIA B200 (SM100), PyTorch 2.13.0+cu130, cuDNN 9.26, and nvidia-cutlass-dsl 4.7.0. Both direct arms consume the same contiguous [1, T, D] BF16 input, implement width-four causal depthwise convolution plus SiLU, and write caller-preallocated output. Each number is the median of 15 alternating-order rounds with 10 calls per CUDA-event interval in one process. Ratios are backend NWH / FE, so values above 1 mean FE is faster.

Signature Shape FE execute (us) backend NWH direct (us) Direct ratio FE active (us) backend NWH active (us) Active ratio
bias=None T8192 D8192 75.331 133.802 1.776x 74.335 132.570 1.783x
bias=None T16384 D8192 141.402 263.123 1.861x 140.698 263.011 1.869x
bias=None T32768 D8192 273.363 519.648 1.901x 274.246 518.845 1.892x
bias=None T16384 D12288 213.850 442.186 2.068x 213.856 442.225 2.068x

A separate same-process torch.profiler/CUPTI pass found exactly one kernel per arm per call and reproduced the CUDA-event ratios closely. This corroborates a kernel-throughput advantage rather than wrapper allocation or host-enqueue overhead. The profiler route was the FE vec8 kernel versus cudnn_causal_conv1d_nwh_fwd_k4_silu_cutlass__bfloat16_t. All shapes passed an independent FP32 reference; maximum absolute error divided by the reference range was below 0.00343.

For bias=None, FE compiles the bias load/add out; the backend's public no-bias path supplies the all-zero bias buffer required by its ABI. A second equal-layout current-head run with a real nonzero BF16 bias gives the following signature-level result:

Signature over the same four shapes Direct NWH / FE range CUPTI active NWH / FE range Status
bias=None 1.776-2.068x 1.783-2.068x reproduces the original rounded 1.8-2.1x result
nonzero bias 1.619-1.916x 1.631-1.914x correct and still faster; bias specialization is a follow-up optimization

The original 1.8-2.1x statement therefore applies specifically to bias=None; it is not used as a blanket claim for the nonzero-bias specialization.

FLA interoperability baseline

Measured on one NVIDIA B200 (SM100), PyTorch 2.13.0+cu130, cuDNN 9.26, nvidia-cutlass-dsl 4.7.0, and FLA 0.5.2. Each number is the median of 21 alternating-order rounds with 5 calls per CUDA-event interval in one process. These rows use bias=None. Ratios are FLA / FE, so values above 1 mean FE is faster.

Shape FE execute (us) FLA direct (us) Direct ratio FE wrapper (us) FLA public (us) Public ratio
dense T8192 D8192 78.483 93.453 1.191x 81.690 100.653 1.232x
dense T16384 D8192 144.710 169.427 1.171x 147.872 174.125 1.178x
dense T32768 D8192 276.499 322.643 1.167x 280.102 326.010 1.164x
dense state+final T16384 D8192 171.712 211.546 1.232x 175.552 214.490 1.222x
packed N8 state+final T16384 D2048 55.827 109.907 1.969x 60.832 136.134 2.238x

These are direct-API CUDA-event elapsed measurements, not profiler-isolated kernel-active cycles or model end-to-end speedups. The FE direct arm uses caller-preallocated outputs while the FLA direct API allocates its outputs internally; the wrapper/public pair is the more symmetric allocation-inclusive comparison. CUDA events may also include device idle gaps while the host enqueues work.

A separate same-process torch.profiler/CUPTI capture isolates active kernel duration after the final stream-lifetime fix. Each implementation ran 20 direct-API plus 20 public-wrapper calls, yielding 40 launches of each kernel:

Shape FE active kernels (us) FLA active kernels (us) Kernel ratio
dense T16384 D8192 vec8 140.339 conv 160.168 1.141x
packed N8 state+final T16384 D2048 vec8 47.652 + validator 1.695 = 49.347 conv 61.089 + state 2.303 = 63.392 1.285x

These profiler ratios are also primitive-only and are intentionally reported separately from API elapsed and any future model-proxy result.

Testing

  • pre-commit run --files <all changed files>: passed (black, black-jupyter; clang-format not applicable).
  • Focused host contract suite after the portable benchmark change: 36 passed.
  • ComputeLab B200 standalone benchmark smoke with SLURM_JOB_ID and SLURMD_NODENAME unset: completed successfully and omitted the optional Slurm object.
  • Final review-fix ComputeLab B200 targeted suite: 36 passed, 1 warning in 35.94s (job 4004734).
  • Current-head B200 equal-layout comparison: all no-bias and nonzero-bias shapes passed the independent FP32 reference; CUDA-event and one-kernel CUPTI ratios agree as reported above.
  • Coverage includes dense/packed scalar and vec8 paths, bias on both schedules, state specializations, exact final-state bits, initial-state immutability, legal packed dynamic-T reuse, explicit/current side-stream allocator lifetime, DLPack alias rejection, and fresh-process device traps for invalid packed metadata.

GitHub CI does not exercise this SM100 GPU runtime path, so the ComputeLab result above is the relevant runtime validation.

Follow-ups are backward support, FLA/Transformers adapters with route proof, conditional cross-API state tests with #797, nonzero-bias specialization tuning, per-architecture tuning beyond the SM100 schedule, and model-proxy measurements after integration.

@YangXu1990uiuc YangXu1990uiuc added cat-feature Requests for new functionality, APIs, examples, or behavior improvements. mod-cutedsl CuTeDSL kernels, generated kernels, examples, or related integration work. mod-frontend cuDNN frontend APIs, operation graph construction, plans, and user-facing wrappers. orig-nv-eng Reported or requested by NVIDIA engineering. labels Aug 29, 2026
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📝 Walkthrough

Walkthrough

Expanded the experimental SM100-suffixed BF16 width-four bulk causal-convolution forward API to supported SM80–SM121 architectures. The change adds scalar and Vec8 kernels, schedule selection, dense and packed stateful execution, public exports, documentation, validation tests, and a B200 benchmark.

Changes

Portable bulk causal-convolution forward

Layer / File(s) Summary
Contract and public surface
docs/fe-oss-apis/causal_conv1d_bulk_contract.md, docs/fe-oss-apis/overview.md, python/cudnn/README.md, python/cudnn/__init__.py, python/cudnn/causal_conv1d_bulk_sm100/__init__.py
Defines dense and packed forward contracts, state semantics, stream behavior, adapter boundaries, delivery status, documentation links, and public exports.
Architecture scheduling and API lifecycle
python/cudnn/_causal_conv1d_bulk_arch.py, python/cudnn/causal_conv1d_bulk_sm100/api.py
Adds supported-capability checks, channel-dependent scalar or Vec8 schedule selection, schedule-specific limits, compilation, runtime validation, and cache specialization.
Scalar and Vec8 kernel execution
python/cudnn/causal_conv1d_bulk_sm100/kernel.py
Adds scalar and Vec8 kernels with packed-boundary validation, causal state recurrence, fused convolution and SiLU computation, and stream-ordered dispatch.
Reference behavior, contract tests, and GPU validation
test/python/fe_api/causal_conv1d_bulk/conftest.py, test/python/fe_api/causal_conv1d_bulk/reference.py, test/python/fe_api/causal_conv1d_bulk/test_causal_conv1d_bulk_contract_unit.py, test/python/fe_api/causal_conv1d_bulk/test_causal_conv1d_bulk_sm100.py, test/python/fe_api/causal_conv1d_bulk/benchmark_causal_conv1d_bulk_sm100.py
Adds PyTorch references and tests for exports, signatures, architecture support, dense and packed execution, state handling, streams, validation, device failures, and B200 performance comparisons.

Estimated code review effort: 4 (Complex) | ~60 minutes

Merge Risk: ⚪ Minimal · up to eb272

This adds an experimental, architecture-gated bulk causal-convolution API with documented validation and no actionable merge-blocking risk remaining beyond normal checks and review.

Sequence Diagram(s)

sequenceDiagram
  participant Caller
  participant causal_conv1d_bulk_fwd_wrapper_sm100
  participant CausalConv1dBulkFwdSm100
  participant CausalConv1dBulkForwardKernel
  Caller->>causal_conv1d_bulk_fwd_wrapper_sm100: Submit dense or packed BF16 tensors and optional state
  causal_conv1d_bulk_fwd_wrapper_sm100->>CausalConv1dBulkFwdSm100: Build or retrieve schedule-specific API
  CausalConv1dBulkFwdSm100->>CausalConv1dBulkForwardKernel: Launch scalar or Vec8 kernel on the selected stream
  CausalConv1dBulkForwardKernel-->>CausalConv1dBulkFwdSm100: Write output and optional final state
  CausalConv1dBulkFwdSm100-->>Caller: Return wrapper output
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❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 21.43% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 56 functions across 10 files. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (4 passed)
Check name Status Explanation
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
Title check ✅ Passed The title is concise and accurately describes the main change: an experimental SM100-optimized bulk causal convolution forward API.
Description check ✅ Passed The description includes all required sections, explains the API and compatibility impact, lists related issues, and provides detailed testing results. The unchecked Projects item is clearly explained…
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The description includes all required sections, explains the API and compatibility impact, lists related issues, and provides detailed testing results. The unchecked Projects item is clearly explained as requiring maintainer action.

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@YangXu1990uiuc YangXu1990uiuc added this to the Frontend 1.29.0 milestone Aug 29, 2026

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Actionable comments posted: 3

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Inline comments:
In `@python/cudnn/causal_conv1d_bulk_sm100/api.py`:
- Around line 130-140: Update the alignment capture in APIBase.__init__ to
record data_ptr() remainders only for framework tensor inputs, skipping
metadata-only TensorDesc values across X, Weight, Output, cu_seqlens, Initial
state, and Final state while preserving the existing alignment widths.

In `@test/python/fe_api/causal_conv1d_bulk/test_causal_conv1d_bulk_sm100.py`:
- Line 162: Update the pytest.raises assertion’s match pattern to use a raw
string while preserving the existing regex and expected error text.
- Around line 546-563: Call _load_class() at the beginning of
test_invalid_cu_seqlens_fail_closed_in_fresh_process so the test inherits the
existing CuTe DSL availability skip gate before launching the subprocess; leave
the worker invocation and assertions unchanged.
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Actionable comments posted: 1

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Inline comments:
In `@python/cudnn/causal_conv1d_bulk_sm100/api.py`:
- Around line 128-129: Update the sample validation around _make_tensor_desc so
required samples sample_x, sample_weight, and sample_output reject None while
preserving None for optional samples. Ensure invalid required inputs raise the
intended TypeError before constructor data_ptr() access and check_support().
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Comment thread python/cudnn/causal_conv1d_bulk_sm100/api.py
@YangXu1990uiuc YangXu1990uiuc changed the title Add experimental SM100 bulk causal conv1d forward Add experimental SM100-optimized bulk causal conv1d forward Aug 29, 2026
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@cudnn-ci-bot run frost,python_tests

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cudnn-ci-bot commented Sep 1, 2026

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🏁 Pipeline finished

SHA: 678e357
Targets: frost, python_tests
Branch: cudnn-gh/pr-798-678e357
Pipeline: 65569766
Last updated: 2026-09-01 05:49 UTC

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Superseded by #799, which now contains this full-sequence forward implementation together with backward, the semantic API, decode update, and their shared state/architecture contracts.

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cat-feature Requests for new functionality, APIs, examples, or behavior improvements. mod-cutedsl CuTeDSL kernels, generated kernels, examples, or related integration work. mod-frontend cuDNN frontend APIs, operation graph construction, plans, and user-facing wrappers. orig-nv-eng Reported or requested by NVIDIA engineering.

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