Hierarchical implementation and verification of a 12-bit educational microprocessor using VHDL and Quartus schematic design.
The project combines a register-transfer datapath, microprogrammed control unit, data memory, ALU, instruction decoding, and sequencing logic. It was developed as part of the Digital Systems and Hardware Description Languages coursework at Universitat Autònoma de Barcelona (UAB).
This repository contains selected implementation files and technical documentation. Some course-provided, automatically generated, and solution-sensitive files are intentionally not redistributed.
LittleProc is a small educational processor designed to demonstrate the main architectural concepts involved in a programmable digital system.
The implementation is organized around two main subsystems:
- UP — Processing Unit / Datapath
- UC — Microprogrammed Control Unit
The processor uses a 12-bit datapath and combines registers, an ALU, data memory, internal buses, instruction decoding, and a microprogrammed control ROM.
The preserved project was originally created using Quartus II 9.0 SP2 and targeted an Altera Cyclone II EP2C35F672C6 FPGA.
The design was later recovered and successfully synthesized and functionally verified using Quartus II 13.0 SP1.
The top-level system integrates:
- 12-bit processing datapath
- Microprogrammed control unit
- 256 × 12-bit data memory
- 256 × 24-bit control ROM
- Instruction decoder
- Microprogram sequencer
- Status flags
- Control-signal interface between the UC and UP
The control unit generates a 20-bit control vector that drives register loads, bus outputs, memory operations, program-counter control, and ALU operation selection.
The processing unit contains the main processor registers:
- R1
- R2
- IR — Instruction Register
- PC — Program Counter
- MAR — Memory Address Register
- MDR — Memory Data Register
- ACC — Accumulator
The registers are interconnected through internal buses and tri-state-controlled data paths.
The ALU operates on 12-bit values and provides processor status information including:
- Zero
- Carry
- Negative
The datapath exchanges instruction opcode and status information with the control unit while receiving the control signals required for each micro-operation.
The UC implements the processor control flow using a microprogrammed architecture.
Its main blocks include:
- Instruction decoder
- Microprogram counter
- Microinstruction sequencer
- Sequencer control logic
- 256 × 24-bit control ROM
The instruction decoder maps the current instruction opcode to the corresponding microprogram entry point.
The sequencer determines the next microinstruction address using the current microprogram state and processor conditions such as zero, carry, and negative.
The project uses a combination of:
- VHDL
- Quartus Block Diagram Files (
.bdf) - Quartus-generated memory and multiplexer components
- Memory Initialization Files (
.mif)
The architecture and expected processor behavior were defined by the course material. My work involved implementing and integrating the specified processor architecture in Quartus, developing selected HDL blocks, constructing schematic modules, and verifying the resulting system.
The repository intentionally contains only a subset of the original implementation.
src/ contains selected VHDL written during the project.
schematics/ contains representative Quartus schematic modules demonstrating sequential and control logic implementation.
The complete processor integration files, course-provided HDL, generated Quartus IP, and full microprogram are not redistributed because the project originates from university coursework that remains relevant to the current course.
The recovered design was successfully analyzed and synthesized using:
- Quartus II 13.0 SP1
- Cyclone II
- EP2C35F672C6
The recovered project completed Analysis & Synthesis with 0 errors.
Functional verification was then performed using a short processor program covering:
- Jump / control-flow operation
- Register load from memory
- ALU addition
- Store to memory
- Load back from memory
- Program termination
The test used:
RAM[18] = 9
RAM[19] = 7
The processor executed the equivalent sequence:
JMP 11
LDR1 18
LDR2 19
ADD
STR1 20
LDR2 20
END
The observed register evolution was:
R1: 0 → 9 → 16
R2: 0 → 7 → 16
The final stored result was therefore:
9 + 7 = 16
The value was written to memory, loaded back into R2, and the processor subsequently decoded the END instruction and asserted the end signal.
More details about the recovery and verification procedure are available in verification/README.md.
The recovered project demonstrated:
- Successful synthesis of the hierarchical processor design
- Correct instruction fetch and decoding
- Correct jump execution
- Correct register loads
- Correct 12-bit ALU addition
- Correct memory store/load behavior
- Correct execution of the final
ENDinstruction
The verification sequence produced the expected final state:
R1 = 16
R2 = 16
END = 1
.
├── README.md
│
├── src/
│ └── reg.vhd
│
├── schematics/
│ ├── PC.bdf
│ ├── microPC.bdf
│ └── ctrlSeq.bdf
│
├── verification/
│ └── README.md
│
└── docs/
└── images/
├── architecture-overview.png
├── control-unit-overview.png
├── datapath-overview.png
└── functional-simulation.png
LittleProc is an educational processor architecture used to study digital system design, processor datapaths, and microprogrammed control.
This repository is intended as a technical portfolio artifact, not as a complete solution to the university assignment.
For that reason:
- only selected implementation files are published;
- course-provided HDL is omitted;
- Quartus-generated source/IP is omitted;
- the complete processor schematics are not redistributed;
- the complete microprogram is not redistributed.
The figures are included to document the architecture and demonstrate the work performed without providing a complete reusable assignment solution.
- How a processor can be decomposed into a datapath and control unit with a clearly defined control interface.
- How microprogrammed control translates processor instructions into sequences of register-transfer operations.
- How to combine VHDL modules and hierarchical schematic design in an FPGA development workflow.
- How to verify processor behavior using waveforms, register-state observation, instruction tracing, and memory tests.
- How to debug a recovered digital design by tracing data through the PC, memory, MDR, internal bus, ALU, and instruction register.