README

Repository Overview

This repository contains two top-level hardware designs along with their associated simulation testbenches. Both designs implement a minimal I3C Simplified Address-Mapped (SAM) Network Adapter, based on the MIPI Debug over I3C specification. The goal is to demonstrate a basic, functional example of how the SAM interface can be integrated into hardware designs for debugging or memory access over I3C. For more information, refer to the official specification: MIPI Debug over I3C.

The repository is platform-independent but also includes hardware-specific build scripts targeting the Digilent Arty A7 board. When using this board, ensure external pull-up resistors are connected to the appropriate I3C lines.

Simulation testbenches can be found in the ./sim directory. A Makefile for running simulations with QuestaSim is provided in ./sim_questa. Alternatively, simulations can be run within the Vivado GUI, but note that the project must be built or created in Vivado beforehand.

Top-Level Design: top_mem

• Source: ./hdl/top_mem.vhd
• Testbench: ./sim/tb_top_mem.vhd

This design connects an AXI-based memory to the SAM interface. The memory can be accessed directly through raw I3C commands with the Lauterbach script ./lauterbach_scripts/mem_test.cmm.

The corresponding simulation verifies memory access functionality via I3C transactions.

Top-Level Design: top_riscv

• Source: ./hdl/top_riscv.vhd
• Testbench: ./sim/tb_top_riscv.vhd

This design connects a RISC-V processor core to the SAM interface via an AXI Debug Transport Module (AXI DTM). The core runs a simple ROM-based program that reads values from GPIO inputs and writes them to GPIO outputs.

The script ./lauterbach_scripts/riscv_dbg.cmm enables access and debugging of the RISC-V core via I3C using Lauterbach tools.

The corresponding testbench simulates execution of the ROM code and validates debug communication over I3C.

Usage Instructions

The root Makefile includes a helpful summary of available commands. Run:

make help

Available make targets:
  build           : Build all projects (mem riscv)
  clean           : Remove generated project directories (mem_prj riscv_prj)
  clean-all       : Run 'clean' and 'sim-clean' to fully clean
  sim-compile     : Compile simulation files
  sim-clean       : Clean simulation artifacts
  help            : Show this help message

Per-project targets:
  build-mem      : Build project 'mem'
  program-mem    : Program FPGA for project 'mem'
  open-mem       : Open Vivado GUI for project 'mem'
  sim-tb_top_mem : Run simulation for project 'mem'

  build-riscv      : Build project 'riscv'
  program-riscv    : Program FPGA for project 'riscv'
  open-riscv       : Open Vivado GUI for project 'riscv'
  sim-tb_top_riscv : Run simulation for project 'riscv'

Common Commands

• To simulate the RISC-V testbench:

make sim-tb_top_riscv

• To build the RISC-V design for the Arty A7 board:

make build-riscv

• To open the RISC-V project in Vivado:

make open-riscv

RISC-V Core Source (Generated via Chipyard)

The RISC-V core used in this project was generated using Chipyard version 1.13.0—an open-source RISC-V SoC generator developed at UC Berkeley. The generated source files are included in this repository.

For more details on using Chipyard, refer to the official repository linked above.

Chipyard Configuration and Boot ROM

This section includes the Chipyard configuration for generating the RISC-V core and a simple boot ROM program. The boot ROM contains an assembly routine that performs basic I/O: reading from general-purpose input registers and writing directly to corresponding output registers.

class myConfig32 extends Config
(
	new testchipip.soc.WithNoScratchpads ++
	new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
	new freechips.rocketchip.subsystem.WithNBanks(0) ++
	new freechips.rocketchip.subsystem.WithNoMemPort ++
	new freechips.rocketchip.rocket.With1TinyCore ++
	new chipyard.config.WithNoUART ++
	new chipyard.harness.WithSerialTLTiedOff ++
	new testchipip.serdes.WithNoSerialTL ++
	new chipyard.config.WithDMIDTM ++
	new chipyard.config.WithGPIO(address=0x10010000, width=8) ++
	new chipyard.config.AbstractConfig
)

<chipyard>/generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.S

.section .text.start, "ax", @progbits
.globl _start
_start:
	csrwi 0x7c1, 0       // disable chicken bits
1:
	lui   t0, 0x10010    // Load upper 20 bits of address 0x10010000 into t0
	lw    t1, 0(t0)      // Load word from address 0x10010000 into t1
	srai  t1, t1, 4      // Arithmetic right shift t1 by 4 bits
	addi  t0, t0, 0x0C   // t0 = 0x10010000 + 0x0C = 0x1001000C
	sw    t1, 0(t0)      // Store the shifted result into 0x1001000C
	j 1b                 // Jump back to label 1:

I3C Target IP

Basic I3C communication is handled by the I3C Target IP obtained from the following open-source project: I3C Target Design

License

The HDL software (RTL) is provided with a BSD Open-source free license. The full BSD 3-line License is used, along with some notes from NXP related to this being RTL (HW) and not Software. NOTE: No license under any third-party patent is granted or implied. It is the responsibility of the licensee to obtain any required third-party patent licenses. Note on terms used above:

1. Software and HDL software are used interchangeably.
2. Binary includes FPGA, simulation, and physical forms such as Silicon chips.
3. Clause 2 allows for such notice on a Web page or other electronic form not part of a distribution.

The original BSD source is available from: https://github.com/NXP/i3c-slave-design

Appendix