feat: add Ascend950 URMA combine - #89
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…gate removal Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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Summary
Workloads
BS * K)The operator accepts FP16 expert output and FP16 top-k weights, performs per-route INT8 transport quantization, and writes FP16 combined output.
Performance
Measured on eight Ascend950PR devices.
Production timing uses profiling-free
strictKernelCycleswith 20 warmup rounds and 100 measured rounds. Each launch is reduced using max-core -> max-rank, followed by the median across measured launches.The retained BS128 report excludes the first-launch synchronization gate from charts and kernel KPIs. Raw gate samples remain embedded only for provenance.
Validation
Validated on eight Ascend950PR devices:
test_tilexr_ep_kernel_sourcestest_tilexr_ep_layoutNotes
The
src/comm/udmachanges provide the independent QPs required by the 22 Send AIVs. Builds that do not enable the Ascend950PR EP path retain the existing single-QP default.