dsv4: NEON arm for FP4 expert matmul (fixes #1696 Apple Silicon prefill) - #1730
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bench_fp4_matmul builds the COLI_V4_UNIT_NATIVE_QUANT unit twice — default flags (SIMD arm active) and with EXTRA_CFLAGS=-mno-avx2 (scalar arm) — verifies the two arms agree bit-exactly on seeded data, and times both at the real DeepSeek-V4-Flash expert shapes (w1/w3 [4096→2048], w2 [2048→4096]). Motivation (JustVugg#1696): on x86-64 (Zen 2, gcc 15, -march=x86-64-v3 vs -mno-avx2) the AVX2 batch arm measures 40–75× faster than the scalar arm at those shapes (~141–159 vs ~1.9–3.8 GFLOP/s), with bit-exact identical outputs. This harness reproduces that A/B anywhere and gives arm64 a baseline for the (currently missing) NEON arm. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Port the AVX2 arm's algorithm to NEON so arm64 stops running the scalar #else arm (Apple Silicon prefill ~1.3-1.75 tok/s, issue JustVugg#1696): - vqtbl1q_u8 nibble LUT decode of doubled e2m1 ints, x0.5f un-double - 4x4 float transposes (vtrnq_f32 + vcombine_f32) turning rows column-major - strict (x*w)*scale rounding with separate mul/mul/add, no FMA fusion — bit-exact identical to the scalar and AVX2 arms (0/262144 floats differ) - one x broadcast serves all 4 columns of a group; 4 independent add chains M-series (gcc-15 -O3): 197-211 GFLOP/s at real expert shapes vs scalar ~9-17 GFLOP/s — 18-22x kernel speedup. Repo make check: 1373 tests OK, 0 new warnings vs dev.
…g#1696) Same decode/transpose/accumulate structure as the batch arm; S=1 keeps 4 float32x4 accumulators in registers for the whole 16-row tile. Bit-exact vs the scalar arm (0/2048 differ at I=4096/O=2048), 1.6-1.9x faster than scalar at S=1 (memory-bound at 4 flop/byte), make check green (1373 tests).
…RM runner The bench compared the SIMD and scalar arms only on x86 (-mno-avx2); on arm64 it built one arm and compared nothing. There the scalar build is -march=armv8-a+nosimd, which undefines __ARM_NEON, and a mismatch now exits non-zero. The ARM job runs it at a batch shape and at S=1, so the NEON arms this PR adds are checked on real arm64 on every change.
This was referenced Sep 24, 2026
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What
NEON arms for both FP4 expert kernels, so arm64 stops falling through to the scalar
#elsearms — the root cause of #1696 (Apple Silicon prefill at decode speed).Batch kernel
coli_fp4_matmul_batch_rows16_order(prefill): ports the AVX2 arm's algorithm to NEON —vqtbl1q_u8nibble-LUT decode (doubled e2m1 ints, ×0.5f un-double),vtrnq/vcombine4×4 transposes, strict per-element(x*w)*scalethen add (separate vmul/vmul/vadd — no FMA, no reassociation; the rows16 rounding contract must be preserved).Matvec kernel
coli_fp4_matvec_rows16_order(decode; also used by batch at S==1): same decode/transpose/accumulate structure, 4float32x4_taccumulators held in registers for the whole 16-row tile.Numbers (M-series, gcc-15 -O3, bit-exact vs scalar arm)
Validation
make check: 1373 tests OK (skipped=128) on the patched tree.c/tools/bench_fp4_matmul.{c,sh}(PR tools: FP4 expert matmul microbench (SIMD vs scalar arm, ref #1696) #1727).Reproduce
arm64: builds the NEON arm and reports; x86-64: builds AVX2 arm vs
-mno-avx2scalar. No model files, torch, or GPU needed — CPU-only, ~30 s.Fixes #1696.