SRAM Controller (for CY62138EV30 SRAM family)

This repository contains a cycle-accurate behavioral model of the Cypress CY62138EV30 (2-Mbit, 256K x 8, 45ns Static RAM) and a fully parameterized, dynamic SRAM controller designed to drive it.

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Features

1. CY62138EV30 Behavioral Model (rtl/CY62138EV30.v)

• Accurate Architecture: 256K words × 8 bits (18-bit address bus).
• Timing Accuracy: Models all 45ns speed-grade delays (tAA, tACE, tDOE, tPWE, etc.).
• Write Termination Logic: Correctly implements Datasheet Note 17 (write terminates on the first rising edge of WE_n or CE_n).
• Bus Contention Protection: Safely handles overlapping OE_n and WE_n assertions.
• Power States: Models Active, Standby, and Data Retention modes based on the VCC enable signal.

2. Dynamic SRAM Controller (rtl/sram_controller.v)

• Parameterized Clock Frequency: Accepts CLK_FREQ_MHZ to adapt to any system clock.
• Dynamic Wait-State Calculation: Automatically calculates the required FSM wait states at compile-time to guarantee the SRAM's 45ns tWC/tRC timing constraints are never violated, regardless of the clock speed.
• Glitch-Free Outputs: All SRAM control signals (ce_n, oe_n, we_n) are strictly registered.
• Safe Tri-State Handling: Guarantees data hold time (tHD) by keeping the data bus driven until the FSM safely returns to the IDLE state.

Project Structure

.
├── rtl/
│   ├── CY62138EV30.v       # Behavioral model of the SRAM
│   └── sram_controller.v   # Dynamic SRAM controller RTL
└── targets/
    └── sim/
        ├── filelist.f           # Icarus Verilog filelist
        ├── Makefile             # Simulation build script
        ├── tb_sram_model.v      # Testbench for the SRAM model (Async)
        └── tb_sram_controller.v # Testbench for the Controller + SRAM (Sync)

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Prerequisites

• Icarus Verilog (iverilog, vvp)
• GTKWave (for viewing waveforms)
• make

How to Simulate

The simulation environment uses a multi-level Makefile system. Navigate to the root directory and run:

# Clean previous simulation artifacts
make clean

# Run the desired simulation level
make sim LEVEL=<0, 1, or 2>

Simulation Levels:

• LEVEL=0: Compiles the CY62138EV30 model only (useful for syntax/lint checking).
• LEVEL=1: Runs tb_sram_model.v. Tests the asynchronous SRAM behavioral model in isolation (power-up, read/write, standby, boundary addresses).
• LEVEL=2: Runs tb_sram_controller.v. Instantiates both the controller and the SRAM model. Tests the synchronous controller's FSM, dynamic wait states, and registered outputs at 50 MHz.

Viewing Waveforms

The testbenches are configured to output FST (Fast Signal Trace) waveforms, which are significantly smaller and faster than VCD.

After running a simulation, view the waveforms with:

gtkwave targets/sim/sim.fst

Datasheet Reference

This implementation is based on the Cypress CY62138EV30 MoBL® 2-Mbit Static RAM Datasheet.

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