Parametric ALU (VHDL)

A flexible, N-bit Parametric Arithmetic Logic Unit (ALU) designed in VHDL. This design allows for scalable bit-widths using generics and supports a wide variety of arithmetic and logical operations, including multiplication and signed comparisons.

Features

• Parametric Design: The data width is easily adjustable via the N generic (default is 8-bit).
• Comprehensive Flag Support: Includes Zero, Carry-out, and Overflow flags.
• Signed Arithmetic: Built using the IEEE.NUMERIC_STD library for robust signed integer math.
• Testbench Included: A verification environment is provided to validate core operations like ADD, AND, OR, XOR, and XNOR.

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Instruction Set (Op-Codes)

The ALU uses a 4-bit selection lines (Sel) to perform the following operations:

Sel (Binary)	Operation	Description
0000	ADD	Addition with Carry-in (A + B + Cin)
0001	SUB	Subtraction with Carry-in (A - B - Cin)
0010	MUL	Multiplication (Returns the lower $N$ bits of the result)
0011	1's Comp	Bitwise NOT of input A
0100	2's Comp	Two's complement (negation) of input A
0101	AND	Bitwise AND
0110	OR	Bitwise OR
0111	XOR	Bitwise XOR
1000	XNOR	Bitwise XNOR
1001	SRL	Logical Shift Right (1-bit)
1010	SLL	Logical Shift Left (1-bit)
1011	CMP	Compare: All '1's if equal, 1 if A > B, -1 if A < B

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Hardware Interface

Generics

• N: Integer (Data bus width). Default is 8.

Ports

Port	Direction	Type	Description
A, B	Input	STD_LOGIC_VECTOR(N-1 downto 0)	Operands
Sel	Input	STD_LOGIC_VECTOR(3 downto 0)	Operation Selector
Cin	Input	STD_LOGIC	Carry Input
ALU_Out	Output	STD_LOGIC_VECTOR(N-1 downto 0)	Result
Cout	Output	STD_LOGIC	Carry Output
Zero	Output	STD_LOGIC	High if result is 0
Overflow	Output	STD_LOGIC	Signed arithmetic overflow flag

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Project Structure

• AUL.vhd: The main ALU hardware description.
• testbench.vhd: Testbench file providing stimulus for simulation.

How to Simulate

1. Tooling: Use any standard VHDL simulator (e.g., ModelSim, GHDL, or Vivado).
2. Compile:

   ghdl -a AUL.vhd testbench.vhd

3. Run:

   ghdl -r Parametric_ALU_tb --vcd=wave.vcd

4. View: Open the .vcd file in GTKWave to view the timing diagrams.

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