MIPS Single-Cycle Processor

A modular 32-bit, single-cycle MIPS processor implementation in Verilog. This project simulates a fully functional CPU capable of executing core R-type, I-type, and J-type instructions, following the classic MIPS architecture. The processor is organized as a collection of reusable Verilog modules, mirroring distinct hardware elements found in real-world MIPS CPUs.

🗂 Project Overview

The codebase is organized into the following Verilog modules, each corresponding to a datapath or control component:

File	Description
Circuit.v	Top-level module connecting all subcomponents
ALU.v	Arithmetic Logic Unit for computation
ALUControl.v	ALU operation decoder
Control.v	Main controller, decodes opcodes and issues control signals
Registers.v	Register file (32 x 32-bit registers)
DataMemory.v	Data RAM for load/store instructions
InstructionMemory.v	Stores program code, loads from program.mem
PC.v	Program Counter register
Adder.v	Used for PC update and address calculation
Mux2to1.v	Multiplexers for datapath selection
SignExtend.v	Extends 16-bit immediates to 32-bit
ShiftLeft2.v	Left shifter for branch/jump address offset alignment
TestBanch.v	Testbench for top-level simulation

📝 Supported Instructions

The processor implements a subset of the MIPS instruction set, featuring:

• Arithmetic/Logic: add, sub, and, or, slt
• Immediate Arithmetic: addi
• Memory Operations: lw (load), sw (store)
• Control Flow: beq (branch if equal), j (jump)

You can extend or modify the instruction set by editing the control logic and memory initialization.

🚀 Getting Started

Prerequisites

• Verilog simulator (e.g., ModelSim, QuestaSim, or Icarus Verilog)
• ModelSim project file: SingleCycleProcessor.mpf (included)

Running a Simulation (with ModelSim/QuestaSim)

1. Launch ModelSim and open the project file SingleCycleProcessor.mpf.
2. Compile all Verilog source files (.v).
3. Ensure program.mem is present in the simulation directory (contains hex machine code).
4. Simulate the TestBanch module as the testbench.
5. Run the simulation, for example: run 100ns.

Customizing Programs

To run your own MIPS programs, edit the program.mem file using hexadecimal machine instructions. The processor will load and execute whatever code is present in this file.

📈 Simulation Results

• Waveform Files:
  • mips_test.vcd: VCD-format output for external waveform viewers
  • vsim.wlf: ModelSim-specific waveform output
• Signal Monitoring:
  • Recommended signals: ALU_Result, pc_current, write_data_reg

These outputs allow you to inspect datapath values, trace program execution, and verify correct processor operation.

⚙️ Additional Notes

• Register $0: Always hardwired to zero per MIPS standard.
• Memory Addressing: Both data and instruction memories are word-addressed (address[31:2]).
• Reset Logic: Activate the reset input in the testbench to initialize the program counter.

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Feel free to fork, modify, or extend this project to experiment with additional MIPS features or to learn about computer architecture design!