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72cbe9e
cuda : record HC affine fusion source prerequisites
GenerelSchwerz Oct 6, 2026
aed72ff
cuda : fuse tensor affine gates with HC postprocessing
GenerelSchwerz Oct 6, 2026
442e724
cuda : compose HC prepared-image review prerequisites
GenerelSchwerz Oct 6, 2026
f04864e
cuda : preserve prepared images during affine HC fusion
GenerelSchwerz Oct 6, 2026
c2de3b5
cuda : fold affine HC gates into prepared image writers
GenerelSchwerz Oct 6, 2026
78b4959
cuda : fold affine HC gates through RMS SCALE terminals
GenerelSchwerz Oct 6, 2026
d355462
cuda : fuse cuBLAS output conversion with gated HC reduction
GenerelSchwerz Oct 6, 2026
6c02602
cuda : fuse cuBLAS result conversion with scalar activation
GenerelSchwerz Oct 6, 2026
3df94da
cuda : fold cuBLAS conversion into tensor affine activation
GenerelSchwerz Oct 6, 2026
3335593
cuda : fuse tensor affine gates on cuBLAS result windows
GenerelSchwerz Oct 6, 2026
5973fca
cuda : fuse a second SCALE in tensor affine gates
GenerelSchwerz Oct 6, 2026
ce6ddc9
cuda : fuse ordinary residual MUL and ADD
GenerelSchwerz Oct 6, 2026
0dead34
cuda : fuse repeated residual MUL and ADD
GenerelSchwerz Oct 6, 2026
24e00b6
cuda : fuse ordered stream MUL and ADD
GenerelSchwerz Oct 6, 2026
5fa22f1
cuda : fuse deferred REPEAT and MUL ADD
GenerelSchwerz Oct 6, 2026
76479e8
cuda : fuse products into RMS normalization
GenerelSchwerz Oct 7, 2026
4af8f37
cuda : defer repeat into product RMS normalization
GenerelSchwerz Oct 7, 2026
e7cff2e
cuda : fuse repeat into ADD
GenerelSchwerz Oct 7, 2026
0ea1373
cuda : read repeated matrix banks from compact inputs
GenerelSchwerz Oct 7, 2026
e9f2bfd
cuda : read repeated quantized matrix banks from compact inputs
GenerelSchwerz Oct 7, 2026
7ef1d05
cuda : pack broadcast activation banks once
GenerelSchwerz Oct 7, 2026
8437ebb
cuda : share banked activation images
GenerelSchwerz Oct 7, 2026
b75964f
cuda : emit banked RMS activation images
GenerelSchwerz Oct 7, 2026
15b12ec
cuda : emit banked HC Q8 activation images
GenerelSchwerz Oct 8, 2026
5aab048
cuda : emit banked HC MMQ activation images
GenerelSchwerz Oct 8, 2026
fd417c6
cuda : reuse multiple-layout producer prerequisite for banked HC
GenerelSchwerz Oct 11, 2026
48a2df2
cuda : emit multiple banked HC MMQ activation layouts
GenerelSchwerz Oct 11, 2026
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88 changes: 83 additions & 5 deletions ggml/src/ggml-cuda/dsv4-hc.cu
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
#include "common.cuh"
#include "dsv4-hc.cuh"
#include "convert.cuh"


static constexpr int DSV4_HC = 4;
Expand Down Expand Up @@ -100,10 +101,26 @@ static __global__ void dsv4_hc_comb_f32(
}
}

template <bool gated>
static __global__ void dsv4_hc_pre_f32(
struct ggml_cuda_hc_gate_f32 {
const float * data;
__device__ __forceinline__ float operator()(int64_t i) const { return data[i]; }
};

template <typename T>
struct ggml_cuda_hc_gate_convert {
const T * data;
float * raw;
__device__ __forceinline__ float operator()(int64_t i) const {
const float value = ggml_cuda_cast<float>(data[i]);
raw[i] = value;
return value;
}
};

template <bool gated, typename Gate>
static __device__ __forceinline__ void dsv4_hc_pre_impl(
const float * x,
const float * weights,
const Gate weights,
float * dst,
int64_t n_embd,
int64_t hc,
Expand Down Expand Up @@ -135,16 +152,50 @@ static __global__ void dsv4_hc_pre_f32(
const float xv = x[i0*sx0 + ih*sx1 + it*sx2];
float wv;
if constexpr (gated) {
wv = 1.0f / (1.0f + expf(-weights[i0*sw0 + ih*sw1 + it*sw2]));
wv = 1.0f / (1.0f + expf(-weights(i0*sw0 + ih*sw1 + it*sw2)));
} else {
wv = weights[ih*sw0 + it*sw1];
wv = weights(ih*sw0 + it*sw1);
}
sum += xv * wv;
}

dst[i0*sd0 + it*sd1] = scale * sum;
}

template <bool gated>
static __global__ void dsv4_hc_pre_f32(
const float * x,
const float * weights,
float * dst,
int64_t n_embd,
int64_t hc,
int64_t n_tokens,
int64_t sx0,
int64_t sx1,
int64_t sx2,
int64_t sw0,
int64_t sw1,
int64_t sw2,
int64_t sd0,
int64_t sd1,
float scale) {
dsv4_hc_pre_impl<gated>(
x, ggml_cuda_hc_gate_f32{weights}, dst, n_embd, hc, n_tokens,
sx0, sx1, sx2, sw0, sw1, sw2, sd0, sd1, scale);
}

template <typename T>
static __global__ void dsv4_hc_pre_convert(
const float * x, const void * weights, float * raw, float * dst,
int64_t n_embd, int64_t hc, int64_t n_tokens,
int64_t sx0, int64_t sx1, int64_t sx2,
int64_t sw0, int64_t sw1, int64_t sw2,
int64_t sd0, int64_t sd1, float scale) {
dsv4_hc_pre_impl<true>(
x, ggml_cuda_hc_gate_convert<T>{(const T *) weights, raw}, dst, n_embd, hc, n_tokens,
sx0, sx1, sx2, sw0, sw1, sw2, sd0, sd1, scale);
}

template <bool has_comb>
static __global__ void dsv4_hc_post_f32(
const float * x,
Expand Down Expand Up @@ -272,6 +323,33 @@ void ggml_cuda_op_dsv4_hc_pre(ggml_backend_cuda_context & ctx, ggml_tensor * dst
scale);
}

void ggml_cuda_op_dsv4_hc_pre_convert(ggml_backend_cuda_context & ctx, ggml_type type, const void * weights, ggml_tensor * mm, ggml_tensor * dst) {
const ggml_tensor * x = dst->src[0];
const ggml_tensor * view = dst->src[1];
GGML_ASSERT(type == GGML_TYPE_F16 || type == GGML_TYPE_BF16);
GGML_ASSERT(x->type == GGML_TYPE_F32 && mm->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32);
GGML_ASSERT(ggml_get_op_params_i32(dst, 1) && ggml_is_contiguous(mm) && ggml_is_contiguous(view));

const int64_t nr = x->ne[0]*x->ne[2];
const dim3 block_dims(256, 1, 1);
const dim3 grid_dims((nr + block_dims.x - 1)/block_dims.x, 1, 1);
const ggml_cuda_kernel_launch_params params(grid_dims, block_dims, 0, ctx.stream());
const auto launch = [&](auto tag) {
using T = decltype(tag);
ggml_cuda_kernel_launch(dsv4_hc_pre_convert<T>, params,
(const float *) x->data, weights, (float *) mm->data, (float *) dst->data,
x->ne[0], x->ne[1], x->ne[2],
x->nb[0]/sizeof(float), x->nb[1]/sizeof(float), x->nb[2]/sizeof(float),
view->nb[0]/sizeof(float), view->nb[1]/sizeof(float), view->nb[2]/sizeof(float),
dst->nb[0]/sizeof(float), dst->nb[1]/sizeof(float), ggml_get_op_params_f32(dst, 0));
};
if (type == GGML_TYPE_F16) {
launch(half{});
} else {
launch(nv_bfloat16{});
}
}

void ggml_cuda_op_dsv4_hc_post(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
const ggml_tensor * x = dst->src[0];
const ggml_tensor * residual = dst->src[1];
Expand Down
2 changes: 2 additions & 0 deletions ggml/src/ggml-cuda/dsv4-hc.cuh
Original file line number Diff line number Diff line change
Expand Up @@ -4,3 +4,5 @@
void ggml_cuda_op_dsv4_hc_comb(ggml_backend_cuda_context & ctx, ggml_tensor * dst);
void ggml_cuda_op_dsv4_hc_pre(ggml_backend_cuda_context & ctx, ggml_tensor * dst);
void ggml_cuda_op_dsv4_hc_post(ggml_backend_cuda_context & ctx, ggml_tensor * dst);

void ggml_cuda_op_dsv4_hc_pre_convert(ggml_backend_cuda_context & ctx, ggml_type type, const void * weights, ggml_tensor * mm, ggml_tensor * dst);
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