This repository contains different DUT (Device Under Test) interface solutions compatible with InterconnectIO Box used on the First Test Station (FTS) project.
Each folder represents a specific DUT connection architecture, from PCB-based solutions to mechanical and cable-only fixtures.
For each solution, the source files are available to make it easy for anyone to duplicate and use in their own project.
A complete DUT Cable example is also included to demonstrate how to design and use a cable-based DUT fixture in a production test environment.
The DUT_Board folder contains PCB-based DUT interface boards.
These boards are used when signal conditioning, routing, or active electronics are required between the InterconnectIO system and the DUT.
- Signal buffering and level shifting
- Power conditioning and protection circuits
- High-density signal routing
- DUT interface standardization
- Complex DUT test fixtures
The DUT_Cable_Board folder contains 3D printed mechanical wiring boards that replace traditional PCB fixtures when no electronics are required.
Instead of copper traces, discrete wires and cable harnesses are used to route signals.
- Passive DUT fixtures
- Rapid prototyping fixtures
- Manufacturing cable harness routing
- Modular and serviceable wiring platforms
The DUT_Cable folder contains minimal single-connector cable harnesses for DUTs that require only a limited set of signals and resources.
This solution is used when the DUT does not need the full InterconnectIO P1/P2 connector resource set.
- Low-complexity DUTs
- Dedicated production test fixtures
- Development and debug setups
- Simple power and communication interfaces
The FTS Communication Fixture is built upon the DUT_Cable hardware architecture. It is designed to provide a reliable, streamlined interface for devices utilizing SPI, I2C, and Serial protocols.
This fixture serves as a perfect example of how the First Test Station (FTS) can be adapted for small-scale projects requiring minimal resources while maintaining industrial-grade connectivity.
- J1 Focused Design: Optimized to utilize the high-density digital resources concentrated on the InterconnectIO J1 port.
- Protocol Support: Dedicated routing for I2C (SDA/SCL), SPI (MOSI/MISO/SCK/CS), and UART/Serial.
- 3D Printed Chassis: A rapidly deployable mechanical housing with integrated strain relief to protect wire terminations.
- Electronic ID: Includes a Fixture ID device to enable automatic hardware detection and prevent incorrect assignment.
- Complete Documentation: Full schematics and a detailed Bill of Materials (BOM) are included in this folder.
- OpenTAP Integration: Example test plans are available in the repository to provide a turnkey starting point for automation.
This project is licensed under the MIT License - see the LICENSE file for details.