feat(startup): named weak IRQ handlers for LPC845/LPC804 vector slots - #38
Conversation
Standard CMSIS startup pattern: every chip-level vector slot gets a peripheral-named handler (SPI0_IRQHandler, DMA0_IRQHandler, ...) weak- aliased to Default_Handler, so a sketch or library installs an ISR by defining the strong symbol. Previously all 32 slots pointed at Default_Handler directly, which made ISR-driven drivers (DMA chunk refill, async UART TX) impossible without a RAM vector table — and the Cortex-M0+ has no VTOR, so that would need SYSMEMREMAP plus a reserved SRAM block in every linker script. Slot names follow each chip's IRQn enum in its vendor CMSIS header. LPC845 and LPC804 get full named maps; other variants keep the legacy all-default table (zero behavior change until their maps are added). Reserved slots stay on Default_Handler. Also make the fault-emit NMI_Handler alias weak, matching the no-fault-emit branch: FastLED routes the WWDT warning interrupt to NMI (SYSCON->NMISRC) for pre-reset wedge backtraces and may want to install a WDT-specific report instead of the generic HardFault print. Downstream consumer: FastLED LPC845 ISR-refillable SPI-DMA streaming + async UART TX drivers (FastLED/FastLED#3453 follow-up). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
|
No actionable comments were generated in the recent review. 🎉 ℹ️ Recent review info⚙️ Run configurationConfiguration used: defaults Review profile: CHILL Plan: Pro Run ID: 📒 Files selected for processing (1)
📝 WalkthroughWalkthroughThe vector table in startup_lpc8xx.c is updated to use chip-specific, individually overridable weak IRQ handler symbols for LPC845 and LPC804 variants, replacing the previous scheme where all chip-level IRQ slots pointed to Default_Handler. NMI_Handler's alias is also made weak. ChangesLPC8xx Weak IRQ Handler Mapping
Estimated code review effort: 3 (Moderate) | ~20 minutes Related PRs: None specified. Suggested labels: enhancement, lpc8xx Suggested reviewers: None specified. 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches📝 Generate docstrings
🧪 Generate unit tests (beta)
Thanks for using CodeRabbit! It's free for OSS, and your support helps us grow. If you like it, consider giving us a shout-out. Comment |
Summary
Standard CMSIS startup pattern: every chip-level vector slot gets a peripheral-named handler (
SPI0_IRQHandler,DMA0_IRQHandler,USART1_IRQHandler, ...) weak-aliased toDefault_Handler, so a sketch or library installs an ISR by simply defining the strong symbol.Why
All 32 chip IRQ slots previously pointed at
Default_Handlerdirectly — no way to hook any peripheral interrupt from user code. That blocks ISR-driven drivers entirely: FastLED's next LPC845 work (ISR-refillable SPI-DMA streaming, async UART TX with DMA chunk refill — FastLED/FastLED#3453 follow-up) needsDMA0_IRQHandler. The Cortex-M0+ has no VTOR, so the only alternative is a RAM vector table viaSYSMEMREMAPplus a reserved block at the start of SRAM in every linker script — far more invasive.Scope
IRQnenum (variants/<chip>/LPC8xx.h). Reserved slots keepDefault_Handler.NMI_Handleras a strong alias ofHardFault_Handler, so nothing downstream could override NMI (the no-fault-emit branch was already weak). Now weak in both. FastLED routes the WWDT warning interrupt to NMI viaSYSCON->NMISRCfor pre-reset wedge backtraces (validated on LPC845-BRK silicon 2026-07-02) and may install a WDT-labeled report.Compatibility
Zero behavior change for existing code: every named handler weak-aliases to the same
Default_Handleras before; the table is link-time identical unless a consumer defines a strong override..isr_vectorsize unchanged (48 entries).🤖 Generated with Claude Code
Summary by CodeRabbit