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feat(startup): named weak IRQ handlers for LPC845/LPC804 vector slots - #38

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feat/named-weak-irq-handlers
Jul 2, 2026
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zackees merged 1 commit into
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feat/named-weak-irq-handlers

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@zackees zackees commented Jul 2, 2026 •

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Summary

Standard CMSIS startup pattern: every chip-level vector slot gets a peripheral-named handler (SPI0_IRQHandler, DMA0_IRQHandler, USART1_IRQHandler, ...) weak-aliased to Default_Handler, so a sketch or library installs an ISR by simply defining the strong symbol.

Why

All 32 chip IRQ slots previously pointed at Default_Handler directly — no way to hook any peripheral interrupt from user code. That blocks ISR-driven drivers entirely: FastLED's next LPC845 work (ISR-refillable SPI-DMA streaming, async UART TX with DMA chunk refill — FastLED/FastLED#3453 follow-up) needs DMA0_IRQHandler. The Cortex-M0+ has no VTOR, so the only alternative is a RAM vector table via SYSMEMREMAP plus a reserved block at the start of SRAM in every linker script — far more invasive.

Scope

  • LPC845 + LPC804: full named maps per each chip's vendor CMSIS IRQn enum (variants/<chip>/LPC8xx.h). Reserved slots keep Default_Handler.
  • Other variants (LPC812/LPC824/...): unchanged — legacy all-default table until someone adds their map.
  • NMI weak-alias fix: the fault-emit branch declared NMI_Handler as a strong alias of HardFault_Handler, so nothing downstream could override NMI (the no-fault-emit branch was already weak). Now weak in both. FastLED routes the WWDT warning interrupt to NMI via SYSCON->NMISRC for pre-reset wedge backtraces (validated on LPC845-BRK silicon 2026-07-02) and may install a WDT-labeled report.

Compatibility

Zero behavior change for existing code: every named handler weak-aliases to the same Default_Handler as before; the table is link-time identical unless a consumer defines a strong override. .isr_vector size unchanged (48 entries).

🤖 Generated with Claude Code

Summary by CodeRabbit

  • Bug Fixes
    • Improved interrupt handling on LPC8xx boards so chip-specific IRQs now map to the correct handlers instead of all falling back to a generic default.
    • Made the non-maskable interrupt handler overrideable, allowing sketches and libraries to provide their own behavior.
    • Preserved default behavior for reserved or unsupported interrupt slots on other chips.

Standard CMSIS startup pattern: every chip-level vector slot gets a
peripheral-named handler (SPI0_IRQHandler, DMA0_IRQHandler, ...) weak-
aliased to Default_Handler, so a sketch or library installs an ISR by
defining the strong symbol. Previously all 32 slots pointed at
Default_Handler directly, which made ISR-driven drivers (DMA chunk
refill, async UART TX) impossible without a RAM vector table — and the
Cortex-M0+ has no VTOR, so that would need SYSMEMREMAP plus a reserved
SRAM block in every linker script.

Slot names follow each chip's IRQn enum in its vendor CMSIS header.
LPC845 and LPC804 get full named maps; other variants keep the legacy
all-default table (zero behavior change until their maps are added).
Reserved slots stay on Default_Handler.

Also make the fault-emit NMI_Handler alias weak, matching the
no-fault-emit branch: FastLED routes the WWDT warning interrupt to NMI
(SYSCON->NMISRC) for pre-reset wedge backtraces and may want to install
a WDT-specific report instead of the generic HardFault print.

Downstream consumer: FastLED LPC845 ISR-refillable SPI-DMA streaming +
async UART TX drivers (FastLED/FastLED#3453 follow-up).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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coderabbitai Bot commented Jul 2, 2026 •

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Review Change Stack

No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info
⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: e803c1cb-31bd-453c-a512-d60f2838f8a8

📥 Commits

Reviewing files that changed from the base of the PR and between fd73dae and 293ea91.

📒 Files selected for processing (1)
  • cores/lpc8xx/startup_lpc8xx.c

📝 Walkthrough

Walkthrough

The vector table in startup_lpc8xx.c is updated to use chip-specific, individually overridable weak IRQ handler symbols for LPC845 and LPC804 variants, replacing the previous scheme where all chip-level IRQ slots pointed to Default_Handler. NMI_Handler's alias is also made weak.

Changes

LPC8xx Weak IRQ Handler Mapping

Layer / File(s) Summary
Weak IRQ handler declarations
cores/lpc8xx/startup_lpc8xx.c
NMI_Handler alias changed to weak; new weak IRQ handler symbols declared for LPC845 and LPC804 chip variants, each aliasing Default_Handler.
Vector table chip-specific mapping
cores/lpc8xx/startup_lpc8xx.c
Vector table IRQ slots conditionally reference the new per-chip weak handlers for LPC845/LPC804, keep reserved slots on Default_Handler, and preserve the legacy all-default mapping for other chips.

Estimated code review effort: 3 (Moderate) | ~20 minutes

Related PRs: None specified.

Suggested labels: enhancement, lpc8xx

Suggested reviewers: None specified.

🚥 Pre-merge checks | ✅ 5
✅ Passed checks (5 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Title check ✅ Passed The title clearly summarizes the main change: named weak IRQ handlers for LPC845/LPC804 startup vector slots.
Docstring Coverage ✅ Passed No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
✨ Finishing Touches
📝 Generate docstrings
  • Create stacked PR
  • Commit on current branch
🧪 Generate unit tests (beta)
  • Create PR with unit tests
  • Commit unit tests in branch feat/named-weak-irq-handlers

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@zackees
zackees merged commit 9e8be02 into main Jul 2, 2026
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@zackees
zackees deleted the feat/named-weak-irq-handlers branch July 2, 2026 14:18
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