Non-Uniform Piecewise Linear Approximation Accelerator for FPGA-based Machine Learning Inference

This repository contains a hardware implementation of a Non-Uniform Piecewise Linear (PWL) approximation accelerator targeting FPGA devices using AMD/Xilinx Vitis HLS and Vitis toolchain.

This repository includes:

• Coefficient generation (Python)
• HLS synthesis and verification
• FPGA deployment targeting AMD Alveo U55C via Vitis v++ flow

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1. Authors

Primary Author

• Patrick Hugo Nepveu Nelson

Supervision

• Jorge Castro-Godínez
• Luis G. León-Vega

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2. Scope

This repository contains the source code supporting the associated thesis published via the Tecnológico de Costa Rica (TEC) repository and the corresponding conference submission. For citations and access to the full text documents, please refer to the primary metadata records listed on the landing page of this DOI repository.

It enables reproduction of:

• Fixed-point PWL coefficient generation
• Functional correctness via HLS simulation
• Hardware synthesis results (latency, II, resource usage)
• FPGA deployment binary generation (.xclbin)

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3. Environment Requirements

System Requirements

• Linux (tested on Ubuntu 22.04)
• Python ≥ 3.8
• AMD/Xilinx Vitis HLS
• AMD/Xilinx Vitis 2024.1 (or compatible)
• Xilinx Runtime (XRT)
• FPGA target: AMD Alveo U55C (required for full hardware reproduction)

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Toolchain Setup (HPC environment)

module load vivado/2024.1
source /opt/hdev/cli/enable/xrt

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Python Environment

cd hls-lut-accelerator
python3 -m venv .venv
source .venv/bin/activate
pip install numpy matplotlib

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4. Repository Structure

.
├── pwl_non_uniform.py        # Coefficient generation
├── pwl_non_uniform.cpp       # HLS kernel
├── pwl_non_uniform_tb.cpp    # Testbench
├── pwl_non_uniform.tcl       # HLS automation script
├── Makefile                  # Full Vitis build flow
└── lut_coeffs.h              # Generated header

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5. Reproduction Instructions

Quick Reproduction (Recommended Entry Point)

make clean
make build

This executes the full FPGA flow from kernel compilation to .xclbin generation.

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Step 1 — Coefficient Generation

cd hls-lut-accelerator
source .venv/bin/activate
python3 pwl_non_uniform.py

Output:

lut_coeffs.h

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Step 2 — HLS Simulation and Synthesis

vitis_hls -f pwl_non_uniform.tcl

This performs:

• C simulation against golden model
• RTL synthesis (Verilog/VHDL generation)
• IP packaging (.xo / Vivado IP)

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Step 3 — FPGA Deployment

module load vivado/2024.1
source /opt/hdev/cli/enable/xrt
make build

Output:

package.hw/kernels.xclbin

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Optional: Platform Selection

make PLATFORM=<platform_name> build

Supported examples:

• xilinx_u55c_gen3x16_xdma_3_202210_1
• xilinx_u280_gen3x16_xdma_1_202211_1
• xilinx_u250_gen3x16_xdma_4_1_202210_1

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6. Evaluation Results

The following results were obtained using the full hardware implementation on AMD Alveo U55C.

Numerical Accuracy (Fixed-Point)

Function	Mode	Input Range	Format	RMSE	Max Error	Status
GELU	Pointwise	[-4, 4]	<16,8>	0.004626	0.012404	PASS
Exponential	Pointwise	[-4, 4]	<32,8>	0.002157	0.004990	PASS
Softmax	Multi-pass	[-4, 4]	<32,8>	0.000132	0.000597	PASS

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7. Reproducibility Notes

• Results depend on selected FPGA platform and Vitis version.
• Timing closure may vary across toolchain versions.
• Kernel frequency is fixed at 200 MHz unless modified in Makefile.
• A clean build is required for correct synthesis results.

If synthesis fails, run:

make cleanall

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8. Expected Build Time

Step	Time Estimate
HLS synthesis	5–20 min
FPGA linking	30–120 min
Full v++ build	1–3 hours

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9. Citation

@misc{pwl_nonuniform_fpga,
  title  = {Design of an HLS-based interpolation unit with configurable multi-access memory for the acceleration of LLM inference on FPGAs},
  author = {Patrick Hugo Nepveu Nelson},
  year   = {2026},
  howpublished = {Zenodo},
  doi    = {10.5281/zenodo.20836965},
  url    = {https://doi.org/10.5281/zenodo.20836965},
  note   = {Source code supporting the Engineering Thesis, Tecnológico de Costa Rica. Hardware validated on AMD Alveo U55C.}
}

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10. License

This project is licensed under the Apache License 2.0.

Copyright 2026 Patrick Hugo Nepveu Nelson

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at:

https://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.