This project focuses on timing analysis for a pre-designed sequential Verilog circuit. The design itself is already provided, so the main goal is to study how timing constraints affect the behavior of a synchronous system and to verify those effects through simulation.
The assignment covers the key timing concepts used in digital design, including clock-to-Q delay, propagation delay, setup time, hold time, clock skew, and slack. It also examines how the critical path determines the minimum clock period and how positive or negative skew can lead to setup or hold violations.
Figure 1 — A diagram of the module under test
A central part of the project is identifying the critical path and determining the minimum clock period required for correct operation. The analysis also includes studying the impact of positive and negative clock skew and understanding how timing margins change under different conditions.
Simulation via ModelSim is used to confirm the manual timing analysis and to observe timing violations when the clock period is reduced or skew is introduced. The final part of the work demonstrates how the design behaves under these different scenarios and how a timing issue can be corrected.
Figure 2 — One of the waveforms in the report (involving run #4)