🏆 WINNER - HARDHACK FORGE 2026
Awarded at PCCOE, Pune, India | January 23, 2026
This repository contains the frontend visualization layer only. The core firmware, signal processing algorithms, and hardware schematics are proprietary.
Uterosync is an award-winning biomedical wearable prototype designed to revolutionize post-operative recovery monitoring. Developed during the 24-hour HardHack Forge hackathon, the system creates a closed-loop monitoring environment for patients and clinicians.
The device utilizes advanced Signal Separation Algorithms to monitor multiple physiological parameters from a single non-invasive sensor point, providing real-time analytics via a driverless web dashboard.
- High-Fidelity Data Acquisition: Processes biopotential signals with <20ms latency using Edge Computing principles.
- Automated Intervention Logic: Features a closed-loop feedback system that triggers therapeutic hardware based on real-time biological thresholding.
- Zero-Install Interface: Utilizes the Web Serial API to render medical-grade data directly in the browser, eliminating the need for hospital IT integration.
- Predictive AI Layer: Implements a forecasting model to predict physiological stress windows, allowing for proactive rather than reactive care.
- Secure Telemetry: End-to-end encrypted alerts sent to clinician mobile devices via IoT protocols.
We utilized a hybrid hardware-software stack to achieve real-time performance.
- React (Vite): For high-performance DOM updates (60fps graphing).
- Recharts: For rendering real-time biological waveforms.
- Tailwind CSS: For a responsive, dark-mode optimized clinical UI.
- Web Serial API: For direct hardware-to-browser communication.
- Microcontroller Architecture: ESP32-based dual-core processing.
- Signal Processing: Custom DSP filtering for noise reduction and artifact removal.
- Actuation: Solid-state control logic for therapeutic modules.
This project was developed by Team Medverse at HardHack Forge 2026 (PCCOE, Pune). We secured the First Place title by demonstrating a functional prototype that successfully performed signal isolation and automated hardware triggering in a live demo environment.
- Dewashish Lambore
- Dhriti Manpurkar
- Revanth Sai Sreerangam
- Sundar Vadivelan Karthikeyan
Due to the potential patentability of the signal processing logic and hardware implementation, source code for the firmware and prediction engine is not publicly available in this repository.