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The ED domain is a faithful mirror of Verilog/VHDL semantics and does not enforce synthesizability. Add a principled note in the processes guide explaining that an edge qualifier belongs in either the sensitivity list or an in-body `if`, but not both for the same signal, with the `process(clk.rising, rst.rising)` async-reset pattern as a worked example. Refs DFHDL#379. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
…x resize
- processes: document that the inline `process(all): stmt` form does not parse;
use braces `process(all) { stmt }` or put the body on the next indented line (#86)
- naming: add a consolidated "Name Collisions & Shadowing" section covering the
Capitalize-design-class convention, the Verilog/VHDL name-preservation caveat,
and `new` / `@targetName` resolution of design-class-vs-value collisions (#87)
- type-system: add a mem(idx.resize) example showing automatic index resize on a
dynamic memory write (#69)
Addresses #86 #87 #69
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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