Update scalafmt-core to 3.11.1

.git-blame-ignore-revs

@@ -0,0 +1,2 @@
+# Scala Steward: Reformat with scalafmt 3.11.1
+f3f023d87a62086c24ee2ef7f638aa6f50ce7785

.scalafmt.conf

@@ -1,4 +1,4 @@
-version = 3.10.7
+version = 3.11.1
 runner.dialect = scala3
 
 maxColumn = 100

compiler/ir/src/main/scala/dfhdl/compiler/analysis/DomainAnalysis.scala

@@ -21,21 +21,24 @@ final class DomainAnalysis(designDB: DB):
             if clkCfg != None || rstCfg != None =>
           collectedDesignDomains.get(key) match
             case Some(clkRstOpt) =>
-              (clkCfg != None && clkRstOpt.clkOpt.isEmpty) || (rstCfg != None && clkRstOpt.rstOpt.isEmpty)
+              (clkCfg != None && clkRstOpt.clkOpt.isEmpty) ||
+              (rstCfg != None && clkRstOpt.rstOpt.isEmpty)
             case None => true
         case _ =>
           setEmpty(key) // TODO: probably ugly to do this here
           false
     private def addClk(key: DFDomainOwner, clk: DFVal.Dcl): Unit =
-      collectedDesignDomains += key -> collectedDesignDomains
-        .get(key)
-        .map(_.addClk(clk))
-        .getOrElse(ClkRstOpt(Some(clk), None))
+      collectedDesignDomains += key ->
+        collectedDesignDomains
+          .get(key)
+          .map(_.addClk(clk))
+          .getOrElse(ClkRstOpt(Some(clk), None))
     private def addRst(key: DFDomainOwner, rst: DFVal.Dcl): Unit =
-      collectedDesignDomains += key -> collectedDesignDomains
-        .get(key)
-        .map(_.addRst(rst))
-        .getOrElse(ClkRstOpt(None, Some(rst)))
+      collectedDesignDomains += key ->
+        collectedDesignDomains
+          .get(key)
+          .map(_.addRst(rst))
+          .getOrElse(ClkRstOpt(None, Some(rst)))
     private def setEmpty(key: DFDomainOwner): Unit =
       collectedDesignDomains += key -> ClkRstOpt(None, None)
   end extension

compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala

@@ -308,14 +308,16 @@ final case class DB(
       }
       // 2. Build port copies (reusing origToDupMap from step 1)
       val pbnsTypes = pbnsByDesign.getOrElse(dupDesign, Map.empty)
-      portEntries += dupDesign -> ListMap.from(origPortMap.getOrElse(origDesign, ListMap.empty).view.map { (name, dcl) =>
-        val dfType = pbnsTypes.getOrElse(name, dcl.dfType)
-        val dupOwnerDomain = origToDupMap(dcl.getOwnerDomain)
-        name -> dcl.copy(ownerRef = DFRef.DuplicationRef(dupOwnerDomain), dfType = dfType)
-      })
+      portEntries += dupDesign ->
+        ListMap.from(origPortMap.getOrElse(origDesign, ListMap.empty).view.map { (name, dcl) =>
+          val dfType = pbnsTypes.getOrElse(name, dcl.dfType)
+          val dupOwnerDomain = origToDupMap(dcl.getOwnerDomain)
+          name -> dcl.copy(ownerRef = DFRef.DuplicationRef(dupOwnerDomain), dfType = dfType)
+        })
     }
     // dupEntries only fills in missing entries (designs without real port members)
     (domainBlockMap.toMap, portEntries.toMap ++ origPortMap)
+  end val
 
   lazy val dupDomainOwnerPublicMemberList: List[(DFDomainOwner, List[DFMember])] =
     def publicMemberFilter(member: DFMember): Boolean =
@@ -348,6 +350,7 @@ final case class DB(
       (dupOwner -> dupMembers) :: origMembers.collect { case db: DomainBlock =>
         dupEntriesFor(db, dupDesign)
       }.flatten
+    end dupEntriesFor
     domainOwnerMemberList.flatMap { case (owner, members) =>
       owner match
         case dupDesign: DFDesignBlock if dupDesign.isDuplicate =>

compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala

@@ -439,8 +439,9 @@ final case class DFStruct(
   def getNameForced: String = name
   def width(using MemberGetSet): Int = fieldMap.values.map(_.width).sum
   def createBubbleData(using MemberGetSet): Data = fieldMap.values.map(_.createBubbleData).toList
-  def isDataBubble(data: Data): Boolean =
-    (fieldMap.values lazyZip data).exists((ft, fd) => ft.isDataBubble(fd.asInstanceOf[ft.Data]))
+  def isDataBubble(data: Data): Boolean = (fieldMap.values lazyZip data).exists((ft, fd) =>
+    ft.isDataBubble(fd.asInstanceOf[ft.Data])
+  )
   def dataToBitsData(data: Data)(using MemberGetSet): (BitVector, BitVector) =
     (fieldMap.values lazyZip data)
       .map((ft, fd) => ft.dataToBitsData(fd.asInstanceOf[ft.Data]))

compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala

@@ -205,16 +205,16 @@ protected trait DFDataPrinter extends AbstractDataPrinter:
   def csDFOpaqueData(dfType: DFOpaque, data: Any): String =
     s"${csConstData(dfType.actualType, data).applyBrackets()}.as(${dfType.name})"
   def csDFStructData(dfType: DFStruct, data: List[Any]): String =
-    dfType.name + dfType.fieldMap
-      .lazyZip(data)
-      .map { case ((n, t), d) =>
-        s"$n = ${csConstData(t, d)}"
-      }
-      .mkStringBrackets
-  def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String =
-    (dfTypes lazyZip data)
-      .map((t, d) => csConstData(t, d))
-      .mkStringBrackets
+    dfType.name +
+      dfType.fieldMap
+        .lazyZip(data)
+        .map { case ((n, t), d) =>
+          s"$n = ${csConstData(t, d)}"
+        }
+        .mkStringBrackets
+  def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String = (dfTypes lazyZip data)
+    .map((t, d) => csConstData(t, d))
+    .mkStringBrackets
   def csDFUnitData(dfType: DFUnit, data: Unit): String = "()"
   def csDFDoubleData(dfType: DFDouble, data: Option[Double]): String =
     data match

compiler/stages/src/main/scala/dfhdl/compiler/stages/AddClkRst.scala

@@ -168,8 +168,7 @@ case object AddClkRst extends Stage:
                 val updatedDFVal = dfVal match
                   // existing clocks also get the constraints from the domain owner
                   case clk: DFVal.Dcl if clk.isClkDcl =>
-                    val updatedAnnotations =
-                      (ownerClkConstraints ++ clk.meta.annotations).distinct
+                    val updatedAnnotations = (ownerClkConstraints ++ clk.meta.annotations).distinct
                     clk.copy(
                       dfType = opaqueReplaceMap(dfType),
                       meta = clk.meta.copy(annotations = updatedAnnotations)

compiler/stages/src/main/scala/dfhdl/compiler/stages/DropStructsVecs.scala

@@ -167,15 +167,17 @@ case object DropStructsVecs extends Stage:
                     case _ => elemIdxVal.asValAny.asInstanceOf[IntParam[Int]]
                   val elemWidth = elemSel.asValAny.widthIntParam
                   val relValWidth = relVal.asValAny.widthIntParam
-                  idxLow = (relValWidth - elemWidth * (elemIdx + 1)) + idxLow
-                    .asInstanceOf[IntParam[Int]]
+                  idxLow = (relValWidth - elemWidth * (elemIdx + 1)) +
+                    idxLow
+                      .asInstanceOf[IntParam[Int]]
                 case rangeSel: DFVal.Alias.ApplyRange =>
                   val elemWidth =
                     replacementMap(relVal).dfType.asInstanceOf[DFVector]
                       .cellType.asFE[DFTypeAny].widthIntParam
                   val relValWidth = relVal.asValAny.widthIntParam
-                  idxLow = (relValWidth - elemWidth * (rangeSel.idxHighRef.get + 1)) + idxLow
-                    .asInstanceOf[IntParam[Int]]
+                  idxLow = (relValWidth - elemWidth * (rangeSel.idxHighRef.get + 1)) +
+                    idxLow
+                      .asInstanceOf[IntParam[Int]]
                 case fieldSel: DFVal.Alias.SelectField =>
                   var relBitLow: IntParam[Int] = idxLow
                   val dfType = replacementMap(relVal).dfType.asInstanceOf[DFStruct]
@@ -205,8 +207,9 @@ case object DropStructsVecs extends Stage:
               case _: DFStruct => false
               case _           => true
             val bitsMeta = if (requireCast) partial.meta.anonymize else partial.meta
-            val idxHigh: IntParam[Int] =
-              (partial.asValAny.widthIntParam + idxLow - 1).asInstanceOf[IntParam[Int]]
+            val idxHigh: IntParam[
+              Int
+            ] = (partial.asValAny.widthIntParam + idxLow - 1).asInstanceOf[IntParam[Int]]
             val bitsVal =
               dfhdl.core.DFVal.Alias.ApplyRange(
                 relVal.asValOf[Bits[Int]],

compiler/stages/src/main/scala/dfhdl/compiler/stages/GlobalizePortVectorParams.scala

@@ -45,8 +45,9 @@ case object GlobalizePortVectorParams extends Stage:
           val dupMember0 = origMember.copyWithNewRefs
           // Tag nested design blocks as duplicates
           val dupMember = dupMember0 match
-            case dsn: DFDesignBlock => dsn.setTags(_.tag(DuplicateTag)).asInstanceOf[dupMember0.type]
-            case _                 => dupMember0
+            case dsn: DFDesignBlock =>
+              dsn.setTags(_.tag(DuplicateTag)).asInstanceOf[dupMember0.type]
+            case _ => dupMember0
           origToDupMemberMap += origMember -> dupMember
           dupRefTable += dupMember.ownerRef -> getReplacement(origMember.getOwner)
           origMember.getRefs.lazyZip(dupMember.getRefs).foreach { (origRef, dupRef) =>
@@ -62,6 +63,7 @@ case object GlobalizePortVectorParams extends Stage:
             duplicateDesignMembers(origNested, dupNested)
           case _ =>
         }
+      end duplicateDesignMembers
       designDB.dupDesignToOrigMap.groupBy(_._2).foreach { (orig, dupMap) =>
         dupMap.keys.foreach { dup => duplicateDesignMembers(orig, dup) }
       }

compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLDataPrinter.scala

@@ -81,12 +81,13 @@ protected trait VHDLDataPrinter extends AbstractDataPrinter:
   def csDFOpaqueData(dfType: DFOpaque, data: Any): String =
     csConstData(dfType.actualType, data)
   def csDFStructData(dfType: DFStruct, data: List[Any]): String =
-    printer.csDFStructTypeName(dfType) + dfType.fieldMap
-      .lazyZip(data)
-      .map { case ((n, t), d) =>
-        s"$n = ${csConstData(t, d)}"
-      }
-      .mkStringBrackets
+    printer.csDFStructTypeName(dfType) +
+      dfType.fieldMap
+        .lazyZip(data)
+        .map { case ((n, t), d) =>
+          s"$n = ${csConstData(t, d)}"
+        }
+        .mkStringBrackets
   def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String = printer.unsupported
   def csDFUnitData(dfType: DFUnit, data: Unit): String = printer.unsupported
   def csDFDoubleData(dfType: DFDouble, data: Option[Double]): String =

compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLValPrinter.scala

@@ -117,10 +117,11 @@ protected trait VHDLValPrinter extends AbstractValPrinter:
               case DFString =>
                 args.map(_.refCodeString).mkString(" & ")
               case dfType @ DFStruct(_, _) =>
-                printer.csDFStructTypeName(dfType) + dfType.fieldMap
-                  .lazyZip(args.map(_.refCodeString))
-                  .map { case ((n, _), d) => s"$n = $d" }
-                  .mkStringBrackets
+                printer.csDFStructTypeName(dfType) +
+                  dfType.fieldMap
+                    .lazyZip(args.map(_.refCodeString))
+                    .map { case ((n, _), d) => s"$n = $d" }
+                    .mkStringBrackets
 
               // all args are the same ==> repeat function
               case _ if args.view.map(_.get).allElementsAreEqual =>

compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala

@@ -278,7 +278,7 @@ class ExplicitNamedVarsSpec extends StageSpec:
   //         shifted ^ o
   //       else shifted
   //     o <> anon.as(AESByte)
-  //   end xtime  
+  //   end xtime
 
   //   val top = (new xtime).explicitNamedVars
   //   assertCodeString(

compiler/stages/src/test/scala/StagesSpec/PrintCodeStringSpec.scala

@@ -1836,7 +1836,8 @@ class PrintCodeStringSpec extends StageSpec:
     class LongChain extends DFDesign:
       val a = UInt(8) <> IN
       val o = UInt(8) <> OUT
-      o <> (a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a)
+      o <>
+        (a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a)
     end LongChain
     val top = (new LongChain).getCodeString
     assertNoDiff(

core/src/main/scala/dfhdl/core/DFDecimal.scala

@@ -108,19 +108,17 @@ object DFDecimal:
           Boolean,
           Boolean,
           [BaS <: Boolean, WcS <: Boolean] =>> BaS || ![WcS],
-          [BaS <: Boolean, WcS <: Boolean] =>>
-            "Cannot apply a signed wildcard `Int` value to " +
-              ITE[BaS, "a signed", "an unsigned"] +
-              " bit-accurate value.\nUse an explicit conversion or `sd\"\"` interpolation."
+          [BaS <: Boolean, WcS <: Boolean] =>> "Cannot apply a signed wildcard `Int` value to " +
+            ITE[BaS, "a signed", "an unsigned"] +
+            " bit-accurate value.\nUse an explicit conversion or `sd\"\"` interpolation."
         ]
     object `BaW >= WcW`
         extends Check2[
           Int,
           Int,
           [BaW <: Int, WcW <: Int] =>> BaW >= WcW,
-          [BaW <: Int, WcW <: Int] =>>
-            "The wildcard `Int` value width (" + WcW +
-              ") is larger than the bit-accurate value width (" + BaW + ")."
+          [BaW <: Int, WcW <: Int] =>> "The wildcard `Int` value width (" + WcW +
+            ") is larger than the bit-accurate value width (" + BaW + ")."
         ]
     type SignStr[S <: Boolean] = ITE[S, "a signed", "an unsigned"]
     object `LS == RS`
@@ -994,6 +992,7 @@ object DFXInt:
                           verilogSemanticsWarnMsg
                         )
                       )
+                    end if
                     val cw: IntParam[Int] = func.op.runtimeChecked match
                       case FuncOp.+ | FuncOp.- => funcWidth + 1
                       case FuncOp.*            => funcWidth + funcWidth
@@ -1008,7 +1007,9 @@ object DFXInt:
                   case Int32 =>
                     lhsCarryPromo.toInt.asIR
                   case BitAccurate =>
-                    DFVal.Alias.AsIs(dfType, lhsCarryPromo)(using dfc.tag(ir.ImplicitlyFromIntTag)).asIR
+                    DFVal.Alias.AsIs(dfType, lhsCarryPromo)(using
+                      dfc.tag(ir.ImplicitlyFromIntTag)
+                    ).asIR
               else if (
                 !dfType.asIR.widthParamRef.isSimilarTo(
                   lhsCarryPromo.dfType.asIR.widthParamRef
@@ -1204,8 +1205,12 @@ object DFXInt:
           // (Int32 NativeType), adapt to the bit-accurate value's sign and width.
           // When both are wildcards, use LS || RS and Max (both-wildcard = DFInt32-like).
           resultSign: Id[ITE[LN && ![RN], RS, ITE[RN && ![LN], LS, ITE[LN && RN, LS, LS || RS]]]],
-          resultWidth: Id[ITE[LN && ![RN], RW, ITE[RN && ![LN], LW,
-            ITE[LN && RN, LW,
+          resultWidth: Id[ITE[LN && ![RN], RW, ITE[
+            RN && ![LN],
+            LW,
+            ITE[
+              LN && RN,
+              LW,
               IntP.Max[
                 ITE[![LS] && RS, LW + 1, LW],
                 ITE[![RS] && LS, RW + 1, RW]
@@ -1223,9 +1228,11 @@ object DFXInt:
           ],
           checkWW: `BaW >= WcW`.Check[
             ITE[RN && ![LN], ubLW.Out, ITE[LN && ![RN], ubRW.Out, ubLW.Out]],
-            ITE[RN && ![LN],
+            ITE[
+              RN && ![LN],
               ITE[LS && ![RS], ubRW.Out + 1, ubRW.Out],
-              ITE[LN && ![RN],
+              ITE[
+                LN && ![RN],
                 ITE[RS && ![LS], ubLW.Out + 1, ubLW.Out],
                 ubLW.Out
               ]
@@ -1287,6 +1294,8 @@ object DFXInt:
                 else
                   arithOp(rhsVal.dfType, op.value, rhsVal, lhsVal)
                     .asInstanceOf[Out]
+              end if
+            end if
           }(using dfc, CTName(op.value.toString))
       end evOpCommutativeArithDFXInt
 
@@ -1324,7 +1333,8 @@ object DFXInt:
           ],
           checkWW: `BaW >= WcW`.Check[
             ITE[LN && ![RN], ubRW.Out, ubLW.Out],
-            ITE[LN && ![RN],
+            ITE[
+              LN && ![RN],
               ITE[RS && ![LS], ubLW.Out + 1, ubLW.Out],
               ubLW.Out
             ]

core/src/main/scala/dfhdl/core/DFEnum.scala

@@ -19,13 +19,11 @@ object DFEncoding:
   abstract class Default extends StartAt(0)
 
   abstract class Gray extends Auto:
-    final def calcWidth(entryCount: Int): Int =
-      (entryCount - 1).bitsWidth(false)
+    final def calcWidth(entryCount: Int): Int = (entryCount - 1).bitsWidth(false)
     final def encode(idx: Int): BigInt = BigInt(idx ^ (idx >>> 1))
 
   abstract class StartAt[V <: Int & Singleton](value: V) extends Auto:
-    final def calcWidth(entryCount: Int): Int =
-      (entryCount - 1 + value).bitsWidth(false)
+    final def calcWidth(entryCount: Int): Int = (entryCount - 1 + value).bitsWidth(false)
     final def encode(idx: Int): BigInt = BigInt(idx + value)
 
   abstract class OneHot extends Auto:

core/src/main/scala/dfhdl/core/DFVal.scala

@@ -809,9 +809,9 @@ object DFVal extends DFValLP:
               args.flatMap {
                 case prevFunc: ir.DFVal.Func
                     if prevFunc.op == op
-                    && prevFunc.isAnonymous
-                    && argCounts(prevFunc) == 1
-                    && canMergeFunc(dfType, op, prevFunc) =>
+                      && prevFunc.isAnonymous
+                      && argCounts(prevFunc) == 1
+                      && canMergeFunc(dfType, op, prevFunc) =>
                   // Track the earliest start position from absorbed Funcs
                   val prevPos = prevFunc.meta.position
                   mergedPositionStart = Some(
@@ -855,13 +855,15 @@ object DFVal extends DFValLP:
     // +, -, * are excluded because carry promotion assumes binary (2-arg) Funcs.
     // ++ is only merged for flat bits concatenation, not struct/vector/string.
     private def canMergeFunc(
-        resultType: ir.DFType, op: FuncOp, prevFunc: ir.DFVal.Func
+        resultType: ir.DFType,
+        op: FuncOp,
+        prevFunc: ir.DFVal.Func
     )(using ir.MemberGetSet): Boolean =
       op match
         case FuncOp.++ =>
           resultType.isInstanceOf[ir.DFBits] && prevFunc.dfType.isInstanceOf[ir.DFBits]
         case FuncOp.+ | FuncOp.- | FuncOp.`*` => false
-        case _ => true // &, |, ^, max, min — no carry concept
+        case _                                => true // &, |, ^, max, min — no carry concept
   end Func
 
   object Alias: